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| SED1352 Graphics LCD Controller SED1352 TECHNICAL MANUAL Document Number: X16B-Q-001-06 Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page ii Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page iii CUSTOMER SUPPORT INFORMATION Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of imbedded graphics systems. Evaluation / Demonstration Board * * Assembled and fully tested graphics evaluation board with installation guide and schematics To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representative Chip Documentation * Technical manual includes Data Sheet, Application Notes, and Programmer's Reference Software * * * * OEM Utilities User Utilities Evaluation Software To obtain these programs, contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by: Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.erd.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 Issue Date: 98/10/08 SED1352 Page iv Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page v TABLE OF CONTENTS INTRODUCTION SED1352 Graphics LCD Controller Data Sheet SPECIFICATION SED1352 Hardware Functional Specification PROGRAMMER'S REFERENCE SED1352 Programming Notes and Examples UTILITIES 1352SHOW.EXE Display Utility VIRTUAL.EXE Display Utility BIOS1352.COM Utility 1352GRAY.EXE Display Utility 1352PD.EXE Power Down Utility 1352READ.EXE Diagnostic Utility EVALUATION SDU1352B0C Rev 1.0 Evaluation Board User Manual APPLICATION NOTES Power Consumption ISA Bus Interface Considerations MC68340 Interface Considerations LCD Panel Options / Memory Requirements Issue Date: 98/10/08 SED1352 Page vi Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date: 98/10/08 GRAPHICS SED1352 October 1998 SED1352 GRAPHICS LCD CONTROLLER s DESCRIPTION The SED1352 is a graphics display LCD controller capable of displaying a maximum of 16 levels of gray on single and dual scan Liquid Crystal Displays. A 16x4 lookup table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel. The SED1352 can interface to the MC68000 microprocessor and 8/16 bit MPUs with READY (WAIT#) signal with minimum external "glue" logic. This chip can directly control up to 128 Kbytes of static SRAM. Optimized for cost and power savings, the SED1352 can operate from 2.7 volts to 5.5 volts and up to 25MHz. s FEATURES * 16-bit 16 MHz MC68000 MPU interface * 8/16-bit MPU interface controlled by a READY (or WAIT#) signal * display memory interface: one 1 Mbit SRAM(64Kx16) one or two 32Kbyte SRAM(s) one or two 8Kbyte SRAM(s) one 8Kbyte and one 32Kbyte SRAM * option to use built-in index register or direct-mapping to access one of fifteen internal registers * 2-terminal crystal input for internal or external crystal oscillator * LCD panel configurations: single-panel, single-drive display dual-panel, dual-drive display * 8/16-bit SRAM interface configurations * two software power-save modes * low power consumption * display modes: 2 bit/pixel, 4-level gray-scale display 4 bit/pixel, 16-level gray-scale display * maximum number of vertical lines: 1,024 lines (single-panel, single-drive display) 2,048 lines (dual-panel, dual-drive display) * split screen display support at single-panel mode * package: QFP5-100-S2 package (F0B) or QFP15-100-STD package (F1B) * virtual display support s SYSTEM BLOCK DIAGRAM CLOCK DATA MPU 80xx Z80 68xxx CONTROL ADDRESS SED1352 LCD PANEL SRAM X16B-C-001-06 1 GRAPHICS SED1352 s INTERFACE OPTIONS Interface with 16-Bit MC68xxx MPU and 16Kbytes SRAM (2 of 8K x 8) MC68xxx A20 to A23 FC0 to FC1 Decoder A16.. A14 Decoder A10 to A19 A1 to A19 D0 to D15 DTACK# UDS# LDS# AS# R/W# IOCS# SED1352 MEMCS# VD8-15 VD0-7 VWE# WE# WE# AB1 to AB19 DB0 to DB15 READY AB0 BHE# IOR# IOW# VCS0# VCS1# VA0-12 64 Kbit CS# 64 Kbit CS# Note: Example implementation, actual may vary. Interface with 8-Bit Z80 MPU and 16Kbytes SRAM (2 of 8K x 8) Z80 MREQ# MI# IORQ# A0 to A15 D0 to D7 WAIT# WR# RD# Decoder SED1352 MEMCS# IOCS# VD0-7 VWE# WE# WE# A10 to A15 Decoder AB0 to AB15 DB0 to DB7 READY MEMW# MEMR# IOR# IOW# RESET 64 Kbit CS# 64 Kbit CS# VCS0# VCS1# VA0-12 RESET# Note: Example implementation, actual may vary. 2 X16B-C-001-06 GRAPHICS SED1352 Interface with 16-Bit 8086 MPU and 64Kbytes SRAM (2 of 32K x 8) 8086 (Maximum mode) CLK CLK READY RESET# RDY CLK 8288 S2# S1# S0# DEN DT/R ALE MRDC# AMWC# IORC# AIOWC# SED1352 MEMR# MEMW# IOR# IOW# VD0-7 VWE# WE# READY RESET# S2# S1# S0# 8284A A16 to A19 256 Kbit AB16 to AB19 CS# VCS0# VA0-14 Decoder M/IO# AB0 to AB15 BHE# MEMCS# IOCS# DB0 to DB15 BHE# AD0 to AD15 A16 BHE# A0 to A16 STB D0 to D15 T OE WE# 256 Kbit CS# VCS1# VD8-15 RESET READY Note: Example implementation, actual may vary. Interface with 8-Bit ISA Bus and 40Kbytes SRAM (1 of 8K x 8 and 1 of 32K x 8) 8-Bit ISA Bus REFRESH SMEMW# SMEMR# IOCHRDY SD0 to SD7 SA0 to SA19 SA10 to SA15 AEN IOW# IOR# RESET# IOW# IOR# RESET WE# SA(1 or 4) to SA9 Decoder IOCS# SA16.. SA13 Decoder SED1352 MEMCS# MEMW# MEMR# READY DB0 to DB7 AB0 to AB19 VCS0# VA0-14 WE# VD0-7 VWE# 64 Kbit CS# optional Decoder VCS1# 256 Kbit CS# 0WS# Note: Example implementation, actual may vary. X16B-C-001-06 3 GRAPHICS SED1352 Interface with 16-Bit ISA Bus and 128Kbytes SRAM (1 of 128K x 8) 16-bit ISA Bus REFRESH SA16.. SA14 SMEMW# SMEMR# IOCHRDY SD0 to SD15 SA0 to SA19 SA10 to SA15 AEN IOW# IOR# SBHE# RESET# IOCS16# LA17 to LA23 MEMCS16# Decoder Decoder Decoder SA(1 or 4) to SA9 IOCS# IOW# IOR# BHE# RESET VD0-7 VD8-15 I/O 1-8 I/O 9-16 Decoder MEMCS# MEMW# MEMR# READY DB0 to DB15 AB0 to AB19 VCS0# VCS1# LB# UB# VWE# WE# SED1352 1 Mbit VA0-15 A0-15 Note: Example implementation, actual may vary. s SUPPORTED RESOLUTIONS Display RAM 8 Kbytes 16 Kbytes 32 Kbytes 40 Kbytes 64 Kbytes 128 Kbytes Example Display Size 4 Grays X Y 16 Grays X Y SRAM Type 1 of 8Kx8 2 of 8Kx8 1 of 32Kx8 1 of 8Kx8 and 1 of 32Kx8 2 of 32Kx8 1 of 64Kx16 CPU Interface 8-bit 8-bit 16-bit 8-bit 8-bit 8-bit 16-bit 16-bit SRAM Interface 8-bit 8-bit/16-bit 16-bit 8-bit 8-bit 8-bit/16-bit 16-bit 16-bit 256 x 128 320 x 200 512 x 256 512 x 320 512 x 512 1024 x 512 128 x 128 200 x 160 256 x 256 320 x 256 512 x 256 512 x 512 4 X16B-C-001-06 GRAPHICS SED1352 s BLOCK DIAGRAM Control Registers IOR#, IOW#, IOCS#, MEMCS#, MEMR#, MEMW#, BHE#, AB[19:0] Bus Signal Translation Port Decoder Memory Decoder Data Bus Conversion Sequence Controller Look-Up Table Address Generator CPU/CRT Selector LCD Panel Interface LCDENB UD[3:0] LD[3:0] LP, YD, WF, XSCL READY DB[15:0] Display Data Formatter Timing Generator Power Save Oscillator OSC1 OSC2 SRAM Interface VWE# VOE# VSC0#, VSC1# VA[15:0] VD[15:0] X16B-C-001-06 5 GRAPHICS SED1352 s FUNCTIONAL BLOCK DESCRIPTIONS Bus Signal Translation According to configuration setting VD2, Bus Signal Translation translates MC68000 type CPU signals, or READY type MPU signals, to internal bus interface signals. Data Bus Conversion According to configuration setting VD0, the Data Bus Conversion maps the external data bus, either 8-bit or 16bit, into the internal odd and even data bus. Control Registers The fifteen internal Control and Configuration Registers are accessed by direct-mapping or by using the built-in internal index register. Address Generator The Address Generator generates display refresh addresses used to access display memory. CPU / CRT Selector Sequence Controller The Sequence Controller generates horizontal and vertical display timings according to the configuration registers settings. The CPU / CRT Selector accesses the display memory from the CPU or the display refresh circuitry. Display Data Formatter The Display Data Formatter reads the display data from the display memory and outputs the correct format for all supported LCD panel types and gray-scale selections. LCD Panel Interface The LCD Interface performs frame rate modulation for passive monochrome LCD panels. Clock Inputs / Timing Look-Up Table The Look-Up Table contains sixteen 4-bit wide palettes that can be configured as one 16x4 palette or four 4x4 palettes used for the re-mapping of gray-scale outputs. Clock Inputs / Timing generates the internal master clock according to the gray-level selected and display memory interface.The master clock (MCLK) can be: MCLK = input clock MCLK = 1/2 input clock MCLK = 1/4 input clock Pixel clock = input clock. Port Decoder According to configuration settings VD1, VD12 - VD4, IOCS# and address lines AB9-1, the Port Decoder validates a given I/O cycle. SRAM Interface The SRAM Interface generates the necessary signals to interface to the Display memory (SRAM). Memory Decoder According to configuration settings VD15 - VD13, MEMCS# and address lines AB19-17, the Memory Decoder validates a given memory cycle. 6 X16B-C-001-06 GRAPHICS SED1352 s DC SPECIFICATIONS Absolute Maximum Ratings Symbol VDD VIN VOUT TSTG TSOL Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time Rating VSS - 0.3 to + 6.5 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 -65 to 150 260 for 10 sec. max at lead Units V V V C C Recommended Operating Conditions Symbol VDD VIN IOPR TOPR PTYP Parameter Supply Voltage Input Voltage Operating Current Operating Temperature Typical Active Power Consumption fOSC = 6 MHz, 16 grays fOSC = 6 MHz, 16 grays -40 Condition VSS = 0V Min 2.7 VSS Typ 3.0/3.3/5.0 -3.0/3.5/7.0 25 9.0/11.55/ 35.0 85 Max 5.5 VDD Units V V mA C mW Input Specifications Symbol VIL Parameter Low Level Input Voltage Condition VDD = 4.5V VDD = 3.0V VDD = 2.7V VDD = 5.5V VDD = 3.6V VDD = 3.3V VDD = 5.0 VDD = 3.3 VDD = 3.0 VDD = 5.0 VDD = 3.3 VDD = 3.0 VDD = 5.0 VDD = 3.3 VDD = 3.0 -Min Typ Max 0.8 0.6 0.5 Units V VIH High Level Input Voltage 2.0 2.5 2.3 2.4 2.4 2.3 0.6 0.6 0.5 0.1 0.1 0.1 -1 1 V VT+ Positive-going Threshold V VT- Negative-going Threshold V VH IIZ Hysteresis Voltage Input Leakage Current V A X16B-C-001-06 7 GRAPHICS SED1352 Output Specifications Symbol Parameter Low Level Output Voltage VOL (5.0V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 Low Level Output Voltage VOL (3.3V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 Low Level Output Voltage VOL (3.0V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 High Level Output Voltage VOH (5.0V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 Low Level Output Voltage VOH (3.3V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 High Level Output Voltage VOH (3.0V) Type 2- TS2, CO2, TS2D2 Type 3- TS3 Type 4- TS4, CO4 Output Leakage Current Output Pin Capacitance Bidirectional Pin Capacitance IOH = -1 mA IOH = -1.8 mA IOH = -3.5 mA VDD-0.3 V A pF pF IOL = -1 mA IOL = -2 mA IOL = -4 mA VDD-0.3 V IOH = -2 mA IOH = -4 mA IOH = -8 mA VDD-0.4 V IOL = 3mA IOL = 5 mA IOL = 10mA VSS + 0.3 V IOL = 3mA IOL = 6mA IOL = 12mA VSS + 0.3 V IOL = 6 mA IOL = 12 mA IOL = 24 mA VSS + 0.4 V Condition Min Typ Max Units IOZ COUT CBID -1 6 10 1 8 X16B-C-001-06 GRAPHICS SED1352 SED1352F0B 51 VD7 52 V 53 SS V 54 DD VD8 55 VD9 56 VD10 57 VD11 58 VD12 59 VD13 60 VD14 61 VD15 62 VA11 63 VA12 64 VA13 65 VA14 66 VA15 67 VWE# 68 VCS0# 69 VCS1# 70 UD3 30 AB18 29 AB17 28 AB16 27 AB15 26 AB14 25 AB13 24 AB12 23 AB11 22 AB10 21 AB9 20 AB8 19 AB7 18 AB6 17 AB5 AB4 16 AB3 15 AB2 14 AB1 13 AB0 12 DB15 11 DB14 10 DB13 9 DB12 8 73 74 75 76 77 78 79 80 UD1 UD0 LD3 LD2 LD1 LD0 YD WF XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 LP DB11 7 DB10 6 DB9 5 DB8 4 VDD 3 VSS 2 DB7 1 71 72 UD2 s SED1352 PIN OUTS VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 X16B-C-001-06 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 9 GRAPHICS SED1352 75 YD 74 73 72 71 70 69 51 VD8 52 VD9 53 VD10 54 VD11 55 VD12 56 VD13 57 VD14 58 VD15 59 VA11 60 VA12 61 VA13 62 VA14 63 VA15 64 VWE# 65 VCS0# 66 VCS1# 67 UD3 68 UD2 LD0 LD1 LD2 LD3 UD0 UD1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 LP WF XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD SED1352F1B VDD VSS VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 AB18 AB17 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AB16 24 AB15 23 AB14 22 AB13 21 AB12 20 AB11 19 AB10 18 AB9 17 AB8 16 AB7 15 AB6 14 AB5 13 AB4 12 AB3 11 AB2 10 AB1 9 AB0 8 DB15 DB14 7 DB11 4 DB10 3 DB13 6 DB12 5 DB9 2 DB8 1 10 X16B-C-001-06 GRAPHICS SED1352 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VA11 VA12 VA13 VA14 VA15 VWE# VCS0# VCS1# UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 YD Dummy Pad 70 LP WF XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD Dummy Pad AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 60 50 VDD VSS VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 AB18 AB17 80 40 SED1352D0B 90 30 100 1 10 20 Chip Size Chip Thickness Pad Size Pad Pitch = = = = 4.400 mm x 4.400 mm 0.400 mm 0.090 mm x 0.090 mm 0.140 mm (Min.) X16B-C-001-06 11 GRAPHICS SED1352 PAD Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 RESET VA0 VA1 VA2 VA3 VA4 VA5 VA6 Pad Center Coordinate X Y -1.850 -2.071 -1.670 -2.071 -1.496 -2.071 -1.330 -2.071 -1.168 -2.071 -1.012 -2.071 -0.860 -2.071 -0.712 -2.071 -0.566 -2.071 -0.423 -2.071 -0.281 -2.071 -0.140 -2.071 0.000 -2.071 0.140 -2.071 0.281 -2.071 0.423 -2.071 0.566 -2.071 0.712 -2.071 0.860 -2.071 1.012 -2.071 1.168 -2.071 1.330 -2.071 1.496 -2.071 1.670 -2.071 1.850 -2.071 2.071 -2.021 2.071 -1.670 2.071 -1.496 2.071 -1.330 2.071 -1.168 2.071 -1.012 2.071 -0.860 2.071 -0.712 2.071 -0.566 2.071 -0.423 2.071 -0.281 Pad No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name VA7 VA8 VA9 VA10 VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VSS VDD VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VA11 VA12 VA13 VA14 VA15 VWE# VCS0# VCS1# UD3 UD2 UD1 UD0 LD3 LD2 Pad Center Coordinate X Y 2.071 -0.140 2.071 0.000 2.071 0.140 2.071 0.281 2.071 0.423 2.071 0.566 2.071 0.712 2.071 0.860 2.071 1.012 2.071 1.168 2.071 1.330 2.071 1.496 2.071 1.670 2.071 1.850 1.850 2.071 1.670 2.071 1.496 2.071 1.330 2.071 1.168 2.071 1.012 2.071 0.860 2.071 0.712 2.071 0.566 2.071 0.423 2.071 0.281 2.071 0.140 2.071 0.000 2.071 -0.140 2.071 -0.281 2.071 -0.423 2.071 -0.566 2.071 -0.712 2.071 -0.860 2.071 -1.012 2.071 -1.168 2.071 -1.330 2.071 12 X16B-C-001-06 GRAPHICS SED1352 Pad No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Pin Name LD1 LD0 YD LP WF XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY Pad Center Coordinate X Y -1.496 2.071 -1.670 2.071 -2.021 2.071 -2.071 1.850 -2.071 1.670 -2.071 1.496 -2.071 1.330 -2.071 1.168 -2.071 1.012 -2.071 0.860 -2.071 0.712 -2.071 0.566 -2.071 0.423 -2.071 0.281 -2.071 0.140 Pad No. 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Pin Name BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD Dummy Pad Dummy Pad Pad Center Coordinate X Y -2.071 0.000 -2.071 -0.140 -2.071 -0.281 -2.071 -0.423 -2.071 -0.566 -2.071 -0.712 -2.071 -0.860 -2.071 -1.012 -2.071 -1.168 -2.071 -1.330 -2.071 -1.496 -2.071 -1.670 -2.071 -1.850 2.071 2.071 -2.071 -2.071 X16B-C-001-06 13 GRAPHICS SED1352 s PIN DESCRIPTION Key A I O I/O P = = = = = Analog Input Output Bidirectional Power Bus Interface F1B Pin # Pin Name Type F0B Pin # D0B Pad Description # DB0-DB15 I/O 94 - 100, 1, 91 - 98, 4 -11 1-8 12 13 - 31 91 84 9 10 - 28 88 81 These pins are connected to the system data bus. In 8-bit bus mode, DB8-DB15 must be tied to VDD. In MC68000 MPU interface, this pin is connected to the Upper Data Strobe (UDS#) pin of MC68000. In other bus interfaces, this pin is connected to the system address bus. These pins are connected to the system address bus. In MC68000 MPU interface, this pin is connected to the Lower Data Strobe (LDS#) pin of MC68000. In other bus interfaces, this pin is the Bus High Enable input for use with 16-bit system. In 8-bit bus mode, tie BHE# input to VDD. Active low input to select one of fifteen internal registers. In MC68000 MPU interface, this pin is connected to the R/W# pin of MC68000. This input pin will define whether the data transfer is a read (active high) or write (active low) cycle. In other bus interfaces, this is the active low input to write data into an internal register. In MC68000 MPU interface, this pin is connected to the AS# pin of MC68000. This input pin will indicate a valid address is available on the address bus. In other bus interfaces, this is the active low input to read data from an internal register. Active low input to indicate the attempt to access the display memory. Active low input to write data to the display memory. This pin should be tied to VDD in an MC68000 MPU interface. Active low input to read data from the display memory. This pin should be tied to VDD in an MC68000 MPU interface. For MC68000 MPU interface, this pin is connected to the DTACK# pin of MC68000 and will be driven low when ever a data transfer is complete. In other bus interfaces, this output is driven low to force the system to insert wait states when needed. READY is placed in a high-impedance (Hi-Z) state after the transfer is completed. RESET I 32 29 Active high input to force all signals to their inactive states. AB0 I AB1-AB19 I BHE# IOCS# I I IOW# I 85 82 IOR# MEMCS# MEMW# MEMR# I I I I 86 87 88 89 83 84 85 86 READY O 90 87 14 X16B-C-001-06 GRAPHICS SED1352 Display Memory Interface F1B Pin # Pin Name Type F0B Pin # D0B Pad Description # These pins are connected to the display memory data bus. For 16-bit interface, VD0-VD7 are connected to the display memory data bus of even byte addresses and VD8-VD15 are connected to the display memory data bus of odd byte addresses. The output drivers of these pins are tri-stated when RESET is high. On the falling edge of RESET the values of VD0-VD15 are latched into the chip to configure various hardware options. VD0-VD15 each have an internal pull-down resistor VA0-VA15 O VCS1# VCS0# VWE# VOE# O O O O 33 - 43, 62 - 66 69 68 67 83 30 - 40 59, 63 66 65 64 80 These pins are connected to the display memory address bus. Active low chip-select output to the second or odd byte address SRAM. Active low chip-select output to the first or even byte address SRAM. Active low output used for writing data to the display memory. This pin is connected to the WE# input of the SRAMs. Active low output to enable reading of data from the display memory. This pin is connected to the OE# input of the SRAMs. VD0-VD15 I/O 44 - 51, 54 - 61 41 - 48, 51 - 58 LCD Interface Pin Name F1B Pin # FPDI-1TM Description a Type F0B Pin # D0B Pad # Pin Name O 70 - 73 67 - 70 Upper panel display data for dual panel mode. For single panel mode, these bits are the most significant 4 bits of the 8 bits output data to the panel (PD[4:7]). For 4-bit single panel mode, these bits are the 4 bits of output data to the panel. Lower panel display data for dual panel mode. For 8-bit single panel mode, these bits are the least significant 4 bits of the 8 bits output data to the panel (PD[0:3]). For 4-bit single panels, these bits are driven 0 (low state). Display data shift clock. Data is shifted into the LCD X-drivers on the falling edge of this signal. Display data latch clock. The falling edge of this signal is used to latch a row of display data in the LCD X-drivers and to turn on the row driver (Y driver). LCD backplane BIAS signal. This output toggles once every n LP periods, as programmed in AUX[5] Vertical scanning start pulse. A logic `1' on this signal, sampled by the LCD module on the falling edge of LP, is used by the panel row driver (Y driver) to indicate the start of the vertical frame. LCD enable signal output. It can be used externally to turn off the panel supply voltage and backlight. UD3-UD0 UD3-UD0 LD3-LD0 LD3-LD0 O 74 - 77 71 - 74 XSCL LP WF YD LCDENB a FPSHIFT FPLINE MOD O O O 81 79 80 78 82 78 76 77 75 79 FPFRAME O O VESA Flat Panel Display Interface Standard (FPDI-1TM) X16B-C-001-06 15 GRAPHICS SED1352 Clock Inputs Pin Name Type F1B Pin # F0B Pin # D0B Pad Description # 92 89 This pin, along with OSC2 is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. This pin, along with OSC1 is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin should be left unconnected. OSC1 I OSC2 O 93 90 Power Supply Pin Name Type VDD VSS P P F0B Pin # 3, 53 2, 52 F1B Pin # Description D0B Pad # 50, 100 49, 99 Voltage supply. Voltage ground. s SUMMARY OF CONFIGURATION OPTIONS Pin Name VD0 VD1 VD2 VD3 value on this pin at falling edge of RESET is used to configure: 1 0 16-bit host bus interface Use direct-mapping for I/O accesses MC68000 MPU interface 8-bit host bus interface Use internal index register for I/O accesses MPU / Bus interface with memory accesses controlled by a READY (WAIT#) signal (1/0) Swap of high and low data bytes in 16-bit bus No byte swap of high and low data bytes in interface 16-bit bus interface Select I/O mapping address bits [1:9]. These nine bits are latched on power-up and are compared to the MPU address bits [1-9]. A valid I/O cycle combined with a valid address will enable the internal I/O decoder. Therefore, both types of I/O mapping are limited to even address boundaries to determine either the absolute or indexed I/O address of the first register. Note that a "valid I/O cycle" includes IOCS# being toggled low. In direct mapping, the base I/O address is selected by VD7-VD12. In indexing, the base I/O address is selected by VD4-VD12. Select memory mapping address bits [1:3]. VD4-VD12 These three bits are latched on power-up and are compared to the MPU address bits [17-19]. A valid memory cycle combined with a valid address will enable the internal memory decoder. As only the three most significant bits of the address are compared, the maximum amount of VD13-VD15 memory supported is 128K bytes. Note that a "valid memory cycle" includes MEMCS# being toggled low. If 128K byte memory is used, it must be mapped at an even address so all 128K bytes is available without a change in state on A17, as this would invalidate the internal compare logic. 16 X16B-C-001-06 GRAPHICS SED1352 Example: If an ISA bus (no byte swap) with memory segment "A" and I/O location 300h are used, the corresponding settings of VD15-VD0 would be: 8-Bit ISA Bus 16-Bit ISA Bus Index Index Direct Mapping Direct Mapping Register Register 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 11 0000 000 11 0000 xxx 11 0000 000 11 0000 xxx 101 101 101 101 Pin Name VD0 VD1 VD2 VD3 VD12-VD4 VD15-VD13 Where x = don't care; 1 = connected to pull-up resistor; 0 = no pull-up resistor. X16B-C-001-06 17 GRAPHICS SED1352 Illustrated below is the display data which is output from the UD0 to UD3 signal pins and the corresponding display on various panels: UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Panel - Top 8-bit Single Panel LD3 LD2 LD1 LD0 Dual Panel - Bottom UD3 UD2 UD1 UD0 4-bit Single Panel s LCD PANEL PIXELS 640 D O TS 1-1 1-2 1-639 2-639 1-640 2-640 2-1 2 -2 240 LINE S UP PER LC D PA N EL 240-1 240-2 24 0 - 639 24 1 - 639 2 4 0 - 640 241-1 241-2 241 - 640 240 LINES (TO P V IE W ) LO W E R LC D P A N E L 480-1 480-2 48 0 - 639 480 - 640 18 X16B-C-001-06 GRAPHICS SED1352 s MONOCHROME PASSIVE STN LCD PANEL INTERFACE 4-BIT SINGLE PANEL LP : 240 PULSES L P : 4 P UL S E S YD LP WF U D [3:0] LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 240 LINE 1 LINE 2 LP WF XSCL: 80 CLOCK PERIODS XSCL UD3 1-1 1 -2 1-5 1-6 1-7 1 -8 1 -317 1 -318 1 -319 UD2 UD1 UD0 1-3 1 -4 1-320 Example Timing for a 320x240 single panel X16B-C-001-06 19 GRAPHICS SED1352 s MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-BIT SINGLE PANEL LP : 480 PU LSE S LP: 4 PULSES YD LP WF U D [3:0], LD [3:0] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 LP WF XSCL:80 CLOCK PERIODS XS CL UD3 UD2 UD1 UD0 LD 3 LD2 LD1 LD 0 1-1 1-2 1-3 1-4 1-5 1-9 1-10 1 -633 1-634 1-63 5 1-11 1-12 1-13 1-636 1-63 7 1-63 8 1-63 9 1-64 0 1-6 1-7 1-14 1-15 1-8 1-16 Example timing for a 640x480 panel 20 X16B-C-001-06 GRAPHICS SED1352 s MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-BIT DUAL PANEL LP : 240 PULSES LP: 2 PULSES YD LP WF U D [3:0], LD [3:0] LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 LP WF XSCL: 160 CLOCK PERIODS XSCL UD3 UD2 UD1 UD0 LD 3 LD2 LD1 LD 0 1 -1 1 -2 1 -5 1-637 1-6 1-638 1-639 1-3 1-4 241-1 1-7 1-8 241-5 1-640 241-637 241-638 241-639 241-640 241-2 2 4 1 -3 2 4 1 -4 241-6 2 4 1-7 2 4 1-8 Example timing for a 640x480 panel X16B-C-001-06 21 GRAPHICS SED1352 s PACKAGE DIMENSIONS QFP5-100PIN-S2 (SED1352) 23.2 0.04 20.0 0.1 80 51 Unit: mm 81 50 Index 100 31 1 0.15 0.05 2.7 0.1 0.65 0.1 0.30 0.1 30 14.0 0.1 0.8 0.1 1.6 0~12 0.35 17.2 0.04 Actual Size 22 X16B-C-001-06 GRAPHICS SED1352 QFP15-100PIN-STD (SED1352F1B) Unit: mm 16.0 0.4 14.0 0.1 75 76 51 50 14.0 0.1 Index 100 1 0.125 0.1 1.4 0.1 0.5 25 26 0.168 0.1 0.1 0.5 0.2 1 16.0 0.4 0~10 Actual Size X16B-C-001-06 23 GRAPHICS SED1352 s COMPREHENSIVE SUPPORT TOOLS Seiko Epson provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems. Documentation * Technical manuals * Evaluation/Demonstration board manual Evaluation/Demonstration Board * Assembled and fully tested Graphics Evaluation/Demonstration board * Schematic of Evaluation/Demonstration board * Parts List * Installation Guide * CPU Independent Software Utilities * Evaluation Software s Application Engineering Support Seiko Epson offers the following services through their Sales and Marketing Network: * Sales Technical Support * Customer Training * Design Assistance CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS: * SED1352 Technical Manual * SDU1352 Evaluation Boards * CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 Copyright (c)1997, 1998 Epson Research and Development, Inc. All rights reserved. VDC Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation. 24 X16B-C-001-06 SED1352 Dot Matrix Graphics LCD Controller Hardware Functional Specification Document Number: X16-SP-001-16 Copyright (c) 1995, 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 1.2 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 2.4 2.5 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 TYPICAL SYSTEM BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . 12 3.1 16-Bit MC68000 MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 MPU with READY (or WAIT#) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.2 ISA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 3.3 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 Bus Signal Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 Sequence Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.4 LCD Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.5 Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.6 Port Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.7 Memory Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.8 Data Bus Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.9 Address Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.10 CPU / CRT Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.11 Display Data Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.12 Clock Inputs / Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.13 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 5 6 7 PINOUT DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PINOUT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . 25 D.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 A.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.1 MC68000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.2 Non-68000, MPU/Bus With READY (or WAIT#) Signal . . . . . . . . . . . . . . . . . 32 7.2 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.1 Recommended Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 4 Epson Research and Development Vancouver Design Center 7.3 Display Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.1 Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3.2 Read Data From Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 LCD Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4.1 4-Bit Single LCD Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4.2 8-Bit LCD Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 HARDWARE REGISTER INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .46 8.1 8.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.2.1 4-Level Gray Shade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.2.2 16-Level Gray Shade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3 Power Save Modes (PSM 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.1 Power Save Mode 1 (PSM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.2 Power Save Mode 2 (PSM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.3.3 Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.3.4 Pin States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9 DISPLAY MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .57 9.1 SRAM Configurations Supported . . . . . . . . . . . . . . . . . . . . . . . . 57 9.1.1 8-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.1.2 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2 SRAM Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2.1 8-Bit Display Memory Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2.2 16-Bit Display Memory Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.3 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.3.1 For Single Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.3.2 For Dual Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.4 9.5 Memory Size Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Memory Size Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10 MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 5 List of Tables Table 4-1: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: Table 5-6: Table 5-7: Table 6-1: Table 6-2: Table 6-3: Table 6-4: Table 7-1: Table 7-2: Table 7-3: Table 7-4: Table 7-5: Table 7-6: Table 7-7: Table 7-8: Table 7-9: SED1352D0A Pad Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Display Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Summary of Power On / Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O and Memory Addressing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 IOW# Timing (68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 IOR# Timing (68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MEMW# Timing (68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MEMR# Timing (68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IOW# Timing (Non-68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IOR# Timing (Non-68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MEMW# Timing (Non-68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MEMR# Timing (Non-68000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 7-10: Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 7-11: Read Data From Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 7-12: 4-Bit Single LCD Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 7-13: 8-Bit LCD Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 8-1: Table 8-2: Table 8-3: Table 8-4: Table 8-5: Table 8-6: Table 8-7: Table 9-1: Table 9-2: Table 9-3: Table 9-4: Table 9-5: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface . . . . . . . . . . . 48 Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface . . . . . . . . . . 48 Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ID Bit Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Pin States in Power Save Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8-Bit Display Memory Interface SRAM Access Time . . . . . . . . . . . . . . . . . . . . . . . . . 61 16-Bit Display Memory Interface SRAM Access Time. . . . . . . . . . . . . . . . . . . . . . . . . 61 Memory Size Requirement: Number of Horizontal Pixels = 640 . . . . . . . . . . . . . . . . . . . . 62 Memory Size Requirement: Number of Horizontal Pixels = 480 . . . . . . . . . . . . . . . . . . . . 63 Memory Size Requirement: Number of Horizontal Pixels = 320 . . . . . . . . . . . . . . . . . . . . 63 Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 7 List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: 16-Bit 68000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8-Bit Mode, Example: Z80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 16-Bit Mode, Example: i8086 (maximum mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8-Bit Mode (ISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 16-Bit Mode (ISA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SED1352F0B Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SED1352F1B Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SED1352D0B Pad Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IOW# Timing (68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 IOR# Timing (68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MEMW# Timing (68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MEMR# Timing (68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IOW# Timing (Non-68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IOR# Timing (Non-68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MEMW# Timing (Non-68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MEMR# Timing (Non-68000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Recommended Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Read Data From Display Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 LCD Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 LCD Interface Pixel/Data Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4-Bit Single Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8-Bit Single Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8-Bit Dual Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . 54 16-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . 55 8-Bit Mode - 8K bytes SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8-Bit Mode - 16K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8-Bit Mode - 32K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8-Bit Mode - 40K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8-Bit Mode - 64K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16-Bit Mode - 16K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16-Bit Mode - 64K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16-Bit Mode - 128K bytes SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Mechanical Drawing QFP5-100pin-S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Mechanical Drawing QFP15-100pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 9 1 INTRODUCTION 1.1 Scope This is the Functional Specification for the SED1352 Dot Matrix Graphic Display LCD Controller Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences; Graphics Subsystem Designers and Software Developers. 1.2 Overview Description This device is designed for products where low cost, low power consumption, and low component count are the major design considerations. This chip operates from 2.7 Volts to 5.5 Volts and up to 25MHz to suit different power consumption, speed and cost requirements. The SED1352 offers a flexible microprocessor interface. The SED1352 is capable of displaying a maximum of 16 levels of gray. A 16x4 Look-Up Table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel. The SED1352 can interface to an MC68000 family microprocessor or an 8/16-bit MPU/Bus with minimum external "glue" logic. This device can directly control up to 128K bytes of static RAM with a 16-bit data path, or up to 64K bytes with an 8-bit data path. Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 10 Epson Research and Development Vancouver Design Center 2 FEATURES 2.1 Technology * * * low power CMOS 2.7 to 5.5 volt operation QFP5-100pin-S2 and QFP15-100 surface mount package 2.2 System * * * * * * * maximum 25MHz input clock (or pixel clock) 2-terminal crystal input for internal oscillator or direct connection to external clock source maximum 16MHz, 16-bit MC68000 MPU interface 8-bit or 16-bit MPU/Bus interface with memory accesses controlled by a READY (or WAIT#) signal option to use built-in index register or direct-mapping to access one of fifteen internal registers 8-bit or 16-bit SRAM data bus interface configurations display memory configurations: * * * * * * * 128K bytes using one 64Kx16 SRAM 128K bytes using two 64Kx8 SRAMs 64K bytes using two 32Kx8 SRAMs 40K bytes using one 8Kx8 and one 32Kx8 SRAM 32K bytes using one 32Kx8 SRAM 16K bytes using two 8Kx8 SRAMs 8K bytes using one 8Kx8 SRAM 2.3 Display Modes * * * * * 2/4 bits-per-pixel, 4/16 level gray shade display modes one 16x4 Look-Up Table provided for gray shade display modes maximum 16 shades of gray split screen display mode (see AUX[0Ah]) virtual display mode (see AUX[0Dh]) SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 11 2.4 Display Support * example resolutions: * * * 640x480 with 4 grays 640x400 with 16 grays passive monochrome LCD panels: * * * 4-bit single (4-bit data transfer) 8-bit single (8-bit data transfer) 8-bit dual (4-bit data transfer for each half panel) 2.5 Power Management * * * two software power-save modes low power consumption panel power control switch (see AUX[01h] bit 4) Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 12 Epson Research and Development Vancouver Design Center 3 TYPICAL SYSTEM BLOCK DIAGRAMS The following figures show typical system implementations of the SED1352. All of the following block diagrams are shown without SRAM or LCD display. Refer to interface specific Application Notes for complete details (X16-AN-xxx-xx). 3.1 16-Bit MC68000 MPU MC68000 A20 to A23 FC0 to FC1 Decoder A16. A14 Decoder A10 to A19 A1 to A19 D0 to D15 DTACK# UDS# LDS# AS# R/W# SED1352 MEMCS# IOCS# AB1 to AB19 DB0 to DB15 READY AB0 BHE# IOR# IOW# Figure 1: 16-Bit 68000 Series (example implementation only - actual may vary) SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 13 3.1.1 MPU with READY (or WAIT#) signal Z80 MREQ# MI# IORQ# A0 to A15 D0 to D7 WAIT# WR# RD# A10 to A15 Decoder SED1352 MEMCS# IOCS# Decoder AB0 to AB15 DB0 to DB7 READY MEMW# MEMR# IOR# IOW# RESET RESET# Figure 2: 8-Bit Mode, Example: Z80 (example implementation only - actual may vary) 8086 (Maximum mode) CLK CLK READY RESET# RDY CLK 8288 S2# S1# S0# DEN DT/R ALE MRDC# AMWC# IORC# AIOWC# SED1352 MEMR# MEMW# IOR# IOW# READY RESET# S2# S1# S0# 8284A A16 to A19 A16 AB16 to AB19 Decoder M/IO# AB0 to AB15 BHE# MEMCS# IOCS# DB0 to DB15 BHE# AD0 to AD15 BHE# A0 to A16 STB D0 to D15 T OE Transceiver RESET READY Figure 3: 16-Bit Mode, Example: i8086 (maximum mode) (example implementation only - actual may vary) Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 14 Epson Research and Development Vancouver Design Center 3.1.2 ISA Bus 8-Bit ISA Bus REFRESH SMEMW# SMEMR# IOCHRDY SD0 to SD7 SA0 to SA19 SA10 to SA15 AEN IOW# IOR# RESET# Decoder SA16 to SA13 Decoder SED1352 MEMCS# MEMW# MEMR# READY DB0 to DB7 AB0 to AB19 IOCS# IOW# IOR# RESET optional Decoder SA(1 or 4) through SA9 0WS# Figure 4: 8-Bit Mode (ISA) (example implementation only - actual may vary ) 16-bit ISA Bus REFRESH SA16 to SA14 SMEMW# SMEMR# IOCHRDY SD0 to SD15 SA0 to SA19 SA10 to SA15 AEN IOW# IOR# SBHE# RESET# IOCS16# LA17 to LA23 MEMCS16# Decoder Decoder Decoder Decoder SED1352 MEMCS# MEMW# MEMR# READY DB0 to DB15 AB0 to AB19 IOCS# IOW# IOR# BHE# RESET SA(1 or 4) through SA9 Figure 5: 16-Bit Mode (ISA) (example implementation only - actual may vary) SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 15 3.2 Internal Block Diagram Control Registers IOR#, IOW#, IOCS#, MEMCS#, MEMR#, MEMW#, BHE#, AB[19:0] Bus Signal Translation Port Decoder Memory Decoder Data Bus Conversion Sequence Controller Look-Up Table Address Generator CPU/CRT Selector LCD Panel Interface LCDENB UD[3:0] LD[3:0] LP, YD, WF, XSCL READY DB[15:0] Display Data Formatter Timing Generator Power Save Oscillator OSC1 OSC2 SRAM Interface VSC0#, VSC1# VOE# VWE# VD[15:0] VA[15:0] Figure 6: Internal Block Diagram 3.3 Functional Block Descriptions 3.3.1 Bus Signal Translation According to configuration setting VD2, Bus Signal Translation translates MC68000 type CPU signals or READY type MPU signals to internal bus interface signals. 3.3.2 Control Registers The fifteen internal Control and Configuration Registers are accessed by direct-mapping or by using the built-in internal index register. 3.3.3 Sequence Controller The Sequence Controller generates horizontal and vertical display timings according to the configuration registers settings. 3.3.4 LCD Panel Interface The LCD Interface performs frame rate modulation for passive monochrome LCD panels. Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 16 Epson Research and Development Vancouver Design Center 3.3.5 Look-Up Table The Look-Up Table contains sixteen 4-bit wide palettes that can be configured as one 16x4 palette, or four 4x4 palettes used for the re-mapping of gray-scale outputs. See "Look-Up Table Architecture" on page 54. 3.3.6 Port Decoder According to configuration settings VD1, VD12 - VD4, IOCS# and address lines AB9-1, the Port Decoder validates a given I/O cycle. 3.3.7 Memory Decoder According to configuration settings VD15 - VD13, MEMCS# and address lines AB19-17, the Memory Decoder validates a given memory cycle. 3.3.8 Data Bus Conversion According to configuration setting VD0, the Data Bus Conversion maps the external data bus, either 8-bit or 16-bit, into the internal odd and even data bus. 3.3.9 Address Generator The Address Generator generates display refresh addresses used to access display memory. 3.3.10 CPU / CRT Selector The CPU / CRT Selector accesses the display memory from the CPU or the display refresh circuitry. 3.3.11 Display Data Formatter The Display Data Formatter reads the display data from the display memory and outputs the correct format for all supported LCD panel types and gray scale selections. 3.3.12 Clock Inputs / Timing Clock Inputs / Timing generates the internal master clock according to the gray-level selected and display memory interface. The master clock (MCLK) can be: - MCLK = input clock - MCLK = 1/2 input clock - MCLK = 1/4 input clock Refer to section 9.2 SRAM Access Time for further details Pixel clock = input clock. 3.3.13 SRAM Interface The SRAM Interface generates the necessary signals to interface to the Display memory (SRAM). SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 17 4 PINOUT DIAGRAM 80 WF LP 79 YD 78 LD0 77 LD1 76 LD2 75 LD3 74 UD0 73 UD1 72 71 51 VD7 52 V 53 SS V 54 DD VD8 55 VD9 56 VD10 57 VD11 58 VD12 59 VD13 60 VD14 61 VD15 62 VA11 63 VA12 64 VA13 65 VA14 66 VA15 67 VWE# 68 VCS0# 69 VCS1# 70 UD3 UD2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 VSS 2 DB7 1 SED1352F0B VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 DB11 7 DB10 6 DB13 9 DB12 8 DB15 11 DB14 10 30 AB18 29 AB17 28 AB16 27 AB15 26 AB14 25 AB13 24 AB12 23 AB11 22 AB10 21 AB9 20 AB8 19 AB7 AB6 18 Note Package type: surface mount QFP5-100pin-S2. Hardware Functional Specification Issue Date: 99/07/28 DB9 5 DB8 4 VDD 3 Figure 7: SED1352F0B Pinout Diagram AB1 13 AB0 12 AB3 15 AB2 14 AB5 17 AB4 16 SED1352 X16-SP-001-16 Page 18 Epson Research and Development Vancouver Design Center 75 YD 74 73 72 71 70 69 51 VD8 52 VD9 53 VD10 54 VD11 55 VD12 56 VD13 57 VD14 58 VD15 59 VA11 60 VA12 61 VA13 62 VA14 63 VA15 64 VWE# 65 VCS0# 66 VCS1# 67 UD3 68 UD2 LD0 LD1 LD2 LD3 UD0 UD1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 LP WF XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD SED1352F1B VDD VSS VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 AB18 AB17 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AB16 24 AB15 23 AB14 22 AB13 21 DB11 4 DB10 3 DB13 6 DB12 5 AB0 9 8 DB15 DB14 7 AB10 AB11 AB12 Note Package type: surface mount QFP15-100pin. DB9 2 DB8 1 Figure 8: SED1352F1B Pinout Diagram AB1 10 AB2 11 AB3 12 AB4 13 AB5 14 AB6 15 AB7 16 AB8 17 AB9 18 19 20 SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 19 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VA11 VA12 VA13 VA14 VA15 VWE# VCS0# VCS1# UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 YD Dummy Pad 70 LP WF XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD Dummy Pad AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 60 50 VDD VSS VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 AB18 AB17 80 40 90 30 100 1 10 20 Chip Size Chip Thickness Pad Size Pad Patch = = = = 4.00 mm x 4.00 mm 0.400 mm 0.090 mm x 90 mm 0.140 mm (Min.) Figure 9: SED1352D0B Pad Diagram Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 20 Epson Research and Development Vancouver Design Center Table 4-1: SED1352D0A Pad Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 RESET VA0 VA1 VA2 VA3 VA4 VA5 VA6 Pad Center Coordinate X Y -1.850 -2.071 -1.670 -2.071 -1.496 -2.071 -1.330 -2.071 -1.168 -2.071 -1.012 -2.071 -0.860 -2.071 -0.712 -2.071 -0.566 -2.071 -0.423 -2.071 -0.281 -2.071 -0.140 -2.071 0.000 -2.071 0.140 -2.071 0.281 -2.071 0.423 -2.071 0.566 -2.071 0.712 -2.071 0.860 -2.071 1.012 -2.071 1.168 -2.071 1.330 -2.071 1.496 -2.071 1.670 -2.071 1.850 -2.071 2.071 -2.021 2.071 -1.670 2.071 -1.496 2.071 -1.330 2.071 -1.168 2.071 -1.012 2.071 -0.860 2.071 -0.712 2.071 -0.566 2.071 -0.423 2.071 -0.281 Pad No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name VA7 VA8 VA9 VA10 VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VSS VDD VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VA11 VA12 VA13 VA14 VA15 VWE# VCS0# VCS1# UD3 UD2 UD1 UD0 LD3 LD2 Pad Center Coordinate X Y 2.071 -0.140 2.071 0.000 2.071 0.140 2.071 0.281 2.071 0.423 2.071 0.566 2.071 0.712 2.071 0.860 2.071 1.012 2.071 1.168 2.071 1.330 2.071 1.496 2.071 1.670 2.071 1.850 1.850 2.071 1.670 2.071 1.496 2.071 1.330 2.071 1.168 2.071 1.012 2.071 0.860 2.071 0.712 2.071 0.566 2.071 0.423 2.071 0.281 2.071 0.140 2.071 0.000 2.071 -0.140 2.071 -0.281 2.071 -0.423 2.071 -0.566 2.071 -0.712 2.071 -0.860 2.071 -1.012 2.071 -1.168 2.071 -1.330 2.071 SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 21 Table 4-1: SED1352D0A Pad Coordinates (Continued) Pad No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Pin Name LD1 LD0 YD LP WF XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY Pad Center Coordinate X Y -1.496 2.071 -1.670 2.071 -2.021 2.071 -2.071 1.850 -2.071 1.670 -2.071 1.496 -2.071 1.330 -2.071 1.168 -2.071 1.012 -2.071 0.860 -2.071 0.712 -2.071 0.566 -2.071 0.423 -2.071 0.281 -2.071 0.140 Pad No. 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Pin Name BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD Dummy Pad Dummy Pad Pad Center Coordinate X Y -2.071 0.000 -2.071 -0.140 -2.071 -0.281 -2.071 -0.423 -2.071 -0.566 -2.071 -0.712 -2.071 -0.860 -2.071 -1.012 -2.071 -1.168 -2.071 -1.330 -2.071 -1.496 -2.071 -1.670 -2.071 -1.850 2.071 2.071 -2.071 -2.071 Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 22 Epson Research and Development Vancouver Design Center 5 PINOUT DESCRIPTION Key: I O I/O P COx TSx TSxD2 TTL TTLS = = = = = = = = = Input Output Bidirectional (Input/Output) Power pin CMOS level output driver, x denotes driver type (see Table 6-4, "Output Specifications," on page 27) Tri-state CMOS level output driver, x denotes driver type (see Table 6-4, "Output Specifications," on page 27) Tri-state CMOS level output driver with pull down resistor (typical values of 100K/200 at 5V/3.0V respectively), x denotes driver type (see Table 6-4, "Output Specifications," on page 27) TTL level input (for VDD = 5.0V, (see Table 6-3, "Input Specifications," on page 26 for VDD = 3.0V and 3.3V) TTL level input with hysteresis Table 5-1: Bus Interface Pin Name Type F0B Pin # F1B/D0B Pin/Pad # Driver TS2 Description These pins are connected to the system data bus. In 8-bit bus mode, DB8-DB15 must be tied to VDD. In MC68000 MPU interface, this pin is connected to the Upper Data Strobe (UDS#) pin of MC68000. In other bus interfaces, this pin is connected to the system address bus. These pins are connected to the system address bus. In MC68000 MPU interface, this pin is connected to the Lower Data Strobe (LDS#) pin of MC68000. In other bus interfaces, this pin is the Bus High Enable input for use with 16-bit system. In 8bit bus mode, tie BHE# input to VDD. Active low input to select one of fifteen internal registers. In MC68000 MPU interface, this pin is connected to the R/W# pin of MC68000. This input pin defines whether the data transfer is a read (active high) or write (active low) cycle. In other bus interfaces, this is the active low input to write data into an internal register. In MC68000 MPU interface, this pin is connected to the AS# pin of MC68000. This input pin indicates a valid address is available on the address bus. In other bus interfaces, this is the active low input to read data from an internal register. Active low input to indicate the attempt to access the display memory. Active low input to write data to the display memory. This pin should be tied to VDD in an MC68000 MPU interface. DB0-DB15 I/O 94 - 100, 1, 91 - 98, 4 -11 1-8 12 13 - 31 9 10 - 28 AB0 I TTL TTL AB1-AB19 I BHE# I 91 88 TTLS IOCS# I 84 81 TTLS IOW# I 85 82 TTLS IOR# I 86 83 TTLS MEMCS# MEMW# I I 87 88 84 85 TTLS TTLS SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 23 Table 5-1: Bus Interface (Continued) Pin Name MEMR# Type F0B Pin # I 89 F1B/D0B Pin/Pad # 86 Driver TTLS Description Active low input to read data from the display memory. This pin should be tied to VDD in an MC68000 MPU interface. For MC68000 MPU interface, this pin is connected to the DTACK# pin of MC68000 and is driven low when ever a data transfer is complete. In other bus interfaces, this output is driven low to force the system to insert wait states when needed. READY is placed in a high impedance (Hi-Z) state after the transfer is completed. RESET I 32 29 TTLS Active high input to force all signals to their inactive states. READY O 90 87 TS3 Table 5-2: Display Memory Interface Pin Name Type F0B Pin # F1B/D0B Pin/Pad # Driver Description These pins are connected to the display memory data bus. For 16bit interface, VD0-VD7 are connected to the display memory data bus of even byte addresses and VD8-VD15 are connected to the display memory data bus of odd byte addresses. The output drivers of these pins are placed in a high impedance state when RESET is high. On the falling edge of RESET the values of VD0-VD15 are latched into the chip to configure various hardware options. VD0-VD15 each have an internal pull-down resistor (see section Table 5-6: on page 25). VA0-VA15 O VCS1# VCS0# VWE# VOE# O O O O 33 - 43, 62 - 66 69 68 67 83 30 - 40 59, 63 66 65 64 80 CO2 CO2 CO2 CO2 CO2 These pins are connected to the display memory address bus. Active low chip-select output to the second or odd byte address SRAM. See Display Memory Interface section for details. Active low chip-select output to the first or even byte address SRAM. See Display Memory Interface section for details. Active low output used for writing data to the display memory. This pin is connected to the WE# input of the SRAMs. Active low output to enable reading of data from the display memory. This pin is connected to the OE# input of the SRAMs. VD0-VD15 I/O 44 - 51, 54 - 61 41 - 48, 51 - 58 TS2D2 Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 24 Epson Research and Development Vancouver Design Center Table 5-3: LCD Interface Pin Name FPDI-1 Type F0B Pin # Pin Namea TM F1B/D0B Pin/Pad # Driver Description Upper panel display data for dual panel mode. For single panel mode, these bits are the most significant 4 bits of the 8-bit output data to the panel (PD[4:7]). For 4-bit single panel mode, these bits are the 4 bits of output data to the panel. Lower panel display data for dual panel mode. For 8-bit single panel mode, these bits are the least significant 4 bits of the 8-bit output data to the panel (PD[0:3]). For 4-bit single panels, these bits are driven 0 (low state). Display data shift clock. Data is shifted into the LCD X-drivers on the falling edge of this signal. Display data latch clock. The falling edge of this signal is used to latch a row of display data in the LCD Xdrivers and to turn on the row driver (Y driver). LCD backplane BIAS signal. This output toggles according to the value programmed in AUX[05h]. Vertical scanning start pulse. A logic `1' on this signal, sampled by the LCD module on the falling edge of LP, is used by the panel row driver (Y driver) to indicate the start of the vertical frame. LCD enable signal output. It can be used externally to turn off the panel supply voltage and backlight. UD3-UD0 UD3-UD0 O 70 - 73 67 - 70 CO4 LD3-LD0 LD3-LD0 O 74 - 77 71 - 74 CO4 XSCL LP WF FPSHIFT FPLINE MOD O O O 81 79 80 78 76 77 CO4 CO4 CO4 YD FPFRAME O 78 75 CO4 LCDENB a O 82 79 CO2 VESA Flat Panel Display Interface Standard (FPDI-1TM) Table 5-4: Clock Inputs Pin Name Type F0B Pin # F1B/D0B Driver Pin/Pad # 89 * Description This pin, along with OSC2, is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source, then this pin is the clock input. This pin, along with OSC1, is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. If an external oscillator is used as a clock source this pin should be left unconnected. OSC1 I 92 OSC2 O 93 90 * Table 5-5: Power Supply Pin Name VDD VSS Type P P F0B Pin # 3, 53 2, 52 F1B/D0B Pin/Pad # 50, 100 49, 99 Driver P P Description Voltage supply. Voltage ground. SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 25 5.1 Summary of Configuration Options The SED1352 requires some configuration information on power-up. This information is provided through the SRAM data lines VD[0...15]. The state of these pins are read on the falling edge of RESET and used to configure the following options: Table 5-6: Summary of Power On / Reset Options Pin Name VD0 VD1 VD2 VD3 value on this pin at falling edge of RESET is used to configure: 1 0 16-bit host bus interface Use direct-mapping for I/O accesses MC68000 MPU interface 8-bit host bus interface Use internal index register for I/O accesses MPU / Bus interface with memory accesses controlled by a READY (WAIT#) signal (1/0) Swap of high and low data bytes in 16-bit bus No byte swap of high and low data bytes in interface 16-bit bus interface Select I/O mapping address bits [1:9]. These nine bits are latched on power-up and are compared to the MPU address bits [1-9]. A valid I/O cycle combined with a valid address will enable the internal I/O decoder. Therefore, both types of I/O mapping are limited to even address boundaries to determine either the absolute or indexed I/O address of the first register. Note that a "valid I/O cycle" includes IOCS# being toggled low. In direct mapping, the base I/O address is selected by VD7-VD12. In indexing, the base I/O address is selected by VD4-VD12. Select memory mapping address bits [1:3]. VD4-VD12 These three bits are latched on power-up and are compared to the MPU address bits [17-19]. A valid memory cycle combined with a valid address will enable the internal memory decoder. As only the three most significant bits of the address are compared, the maximum amount of VD13-VD15 memory supported is 128K bytes. Note that a "valid memory cycle" includes MEMCS# being toggled low. If 128K byte memory is used, it must be mapped at an even address so all 128K bytes is available without a change in state on A17, as this would invalidate the internal compare logic. Note The SED1352 has internal pulldown resistors on these pins and therefore will be pulled down and read on a logic "0" after RESET. If pullup resistors are required refer to Table 6-3, "Input Specifications," on page 26 for pulldown resistor values. Example: If an ISA bus (no byte swap) with memory segment A000h and I/O location 300h are used, the corresponding settings of VD15-VD0 would be: Table 5-7: I/O and Memory Addressing Example Pin Name VD0 VD1 VD2 VD3 VD12-VD4 VD15-VD13 8-Bit ISA Bus 16-Bit ISA Bus Index Index Direct Mapping Direct Mapping Register Register 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 11 0000 000 11 0000 xxx 11 0000 000 11 0000 xxx 101 101 101 101 Where x = don't care; 1 = connected to pull-up resistor; 0 = no pull-up resistor. Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 26 Epson Research and Development Vancouver Design Center 6 D.C. CHARACTERISTICS Table 6-1: Absolute Maximum Ratings Symbol VDD VIN VOUT TSTG TSOL Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time Rating VSS - 0.3 to + 6.5 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 -65 to 150 260 for 10 sec. max at lead Units V V V C C Table 6-2: Recommended Operating Conditions Symbol VDD VIN IOPR TOPR PTYP Parameter Supply Voltage Input Voltage Operating Current Operating Temperature Typical Active Power Consumption fOSC = 6 MHz, 16 grays fOSC = 6 MHz, 16 grays -40 Condition VSS = 0V Min 2.7 VSS Typ 3.0/3.3/5.0 -3.0/3.5/7.0 25 9.0/11.55/35.0 85 Max 5.5 VDD Units V V mA C mW Table 6-3: Input Specifications Symbol VIL Parameter Low Level Input Voltage Condition VDD = 4.5V VDD = 3.0V VDD = 2.7V VDD = 5.5V VDD = 3.6V VDD = 3.3V VDD = 5.0 VDD = 3.3 VDD = 3.0 VDD = 5.0 VDD = 3.3 VDD = 3.0 VDD = 5.0 VDD = 3.3 VDD = 3.0 -Min Typ Max 0.8 0.6 0.5 Units V VIH High Level Input Voltage 2.0 2.5 2.3 2.4 2.4 2.3 0.6 0.6 0.5 0.1 0.1 0.1 -1 1 V VT+ Positive-going Threshold V VT- Negative-going Threshold V VH IIZ Hysteresis Voltage Input Leakage Current V A SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 27 Table 6-3: Input Specifications Symbol CIN RPD RPD RPD Parameter Input Pin Capacitance Pull Down Resistance Pull Down Resistance Pull Down Resistance VDD = 5.0V VI = VDD VDD = 3.3V VI = VDD VDD = 3.0V VI = VDD 50 90 100 Condition Min Typ 4 200 360 400 Max Units pF k k k Table 6-4: Output Specifications Symbol Parameter Low Level Output Voltage VOL (5.0V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 Low Level Output Voltage VOL (3.3V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 Low Level Output Voltage VOL (3.0V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 High Level Output Voltage VOH (5.0V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 Low Level Output Voltage VOH (3.3V) Type 2 - TS2, CO2, TS2D2 Type 3 - TS3 Type 4 - TS4, CO4 High Level Output Voltage VOH (3.0V) Type 2- TS2, CO2, TS2D2 Type 3- TS3 Type 4- TS4, CO4 Output Leakage Current Output Pin Capacitance Bidirectional Pin Capacitance IOH = -1 mA IOH = -1.8 mA IOH = -3.5 mA VDD-0.3 V A pF pF IOL = -1 mA IOL = -2 mA IOL = -4 mA VDD-0.3 V IOH = -2 mA IOH = -4 mA IOH = -8 mA VDD-0.4 V IOL = 3mA IOL = 5 mA IOL = 10mA VSS + 0.3 V IOL = 3mA IOL = 6mA IOL = 12mA VSS + 0.3 V IOL = 6 mA IOL = 12 mA IOL = 24 mA VSS + 0.4 V Condition Min Typ Max Units IOZ COUT CBID -1 6 10 1 Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 28 Epson Research and Development Vancouver Design Center 7 A.C. CHARACTERISTICS Conditions: VDD = 3.0V 10%, 3.3V 10% or VDD = 5.0V 10% TA = -40 C to 85 C Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%) CL = 80pF (Bus/MPU Interface) CL = 100pF (LCD Panel Interface) CL = 20pF (Display Memory Interface) 7.1 Bus Interface Timing 7.1.1 MC68000 Interface Timing Note All input timing parameters are based on a maximum 16MHz bus clock. IOW# Timing AB[9:1] VALID t2 IOCS# AS# t1 R/W t4 INVALID Hi-Z t5 t7 DB[15:0] Hi-Z VALID t8 Hi-Z t6 Hi-Z t3 UDS#/LDS# DTACK# Figure 10: IOW# Timing (68000) Table 7-1: IOW# Timing (68000) Symbol Parameter t1 AB[9:1] valid before AS# falling edge t2 AB[9:1] hold from AS# rising edge t3 t4 t5 t6 t7 t8 IOCS# hold from AS# rising edge UDS#/LDS# valid before AS# rising edge UDS#/LDS# falling edge to DTACK# falling edge AS# rising edge to DTACK# hi-z delay DB[15:0] setup to AS# rising edge DB[15:0] hold from AS# rising edge 20 20 Min 10 20 0 30 40 45 10 10 3V/3.3V Typ Max Min 0 10 0 20 25 25 5V Typ Max Units ns ns ns ns ns ns ns ns SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 29 IOR# Timing AB[9:1] VALID t2b IOCS# t1 AS# t2a UDS#/LDS# INVALID R/W# t3 DTACK# Hi-Z t5 DB[15:0] Hi-Z VALID t7 t6 Hi-Z t4 Hi-Z Figure 11: IOR# Timing (68000) Table 7-2: IOR# Timing (68000) Symbol t1 t2a t2b t3 t4 t5 t6 t7 Parameter AB[9:1] and IOCS# valid before AS# falling edge AB[9:1] hold from AS# rising edge IOCS# hold from AS# rising edge AS# falling edge to DTACK# falling edge AS# rising edge to DTACK# hi-z delay AS# falling edge to DB[15:0] valid DB[15:0] hold from AS# rising edge AS# rising edge to DB[15:0] hi-z delay Min 10 20 0 35 45 80 25 35 3V/3.3V Typ Max Min 0 10 0 25 25 60 20 30 5V Typ Max Units ns ns ns ns ns ns ns ns Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 30 Epson Research and Development Vancouver Design Center MEMW# Timing AB[19:1] MEMCS# t1 AS# VALID t2 UDS#/LDS# INVALID R/W# t4 DTACK# Hi-Z t3 t5 DB[15:0] Hi-Z VALID t6 Hi-Z Hi-Z Figure 12: MEMW# Timing (68000) Table 7-3: MEMW# Timing (68000) Symbol t1 t2 t3 t4 t5 t6 Parameter AB[19:1] and MEMCS# valid before AS# falling edge AB[19:1] and MEMCS# hold from AS# rising edge AS# falling edge to DTACK# falling edge AS# rising edge to DTACK hi-z delay AS# falling edge to DB[15:0] valid DB[15:0] hold from AS# rising edge 0 Min 0 0 3.5 * MCLK + 20 45 120 0 3V/3.3V Typ Max Min 0 0 3.5 * MCLK + 10 22 140 5V Typ Max Units ns ns ns ns ns ns Where MCLK period = 1/fOSC, or 2/fOSC, or 4/fOSC depending on which mode the chip is in. (see section 9.2 and 9.3). SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 31 MEMR# Timing AB[19:1] MEMCS# t1 AS# VALID t2 UDS#/LDS# INVALID R/W# t4 t3 t5 DB[15:0] Hi-Z VALID t7 t6 Hi-Z DTACK# Hi-Z Hi-Z Figure 13: MEMR# Timing (68000) Table 7-4: MEMR# Timing (68000) Symbol t1 t2 t3 t4 t5 t6 t7 Parameter AB[19:1] and MEMCS# valid before AS# falling edge AB[19:1] and MEMCS# hold from AS# rising edge AS# falling edge to DTACK# falling edge AS# rising edge to DTACK# hi-z delay DTACK# falling edge to DB[15:0] valid DB[15:0] hold from AS# rising edge AS# rising edge to DB[15:0] hi-z delay 3V/3.3V Min Typ Max 0 0 3.5 * MCLK + 20 42 20 54 60 Min 0 0 3.5 * MCLK + 10 20 20 28 30 5V Typ Max Units ns ns ns ns ns ns ns Where MCLK period = 1/fOSC, or 2/fOSC, or 4/fOSC depending on which mode the chip is in. (see section 9.2 and 9.3). Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 32 Epson Research and Development Vancouver Design Center 7.1.2 Non-68000, MPU/Bus With READY (or WAIT#) Signal IOW# Timing AB[9:0] BHE# VALID IOCS# t1 IOW# t3 DB[15:0] Hi-Z VALID t4 Hi-Z t5 t2 Figure 14: IOW# Timing (Non-68000) Table 7-5: IOW# Timing (Non-68000) Symbol t1 t2 t3 t4 t5 Parameter AB[9:0], BHE# and IOCS# valid before IOW# falling edge AB[9:0], BHE# and IOCS# hold from IOW# rising edge DB[15:0] setup to IOW# rising edge DB[15:0] hold from IOW# rising edge Pulse width of IOW# 3V/3.3V Min Typ Max 10 20 20 20 30 Min 0 10 10 10 20 5V Typ Max Units ns ns ns ns SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 33 IOR# Timing AB[9:0] BHE# VALID IOCS# t1 IOR# t3 DB[15:0] Hi-Z VALID t2 t4 Hi-Z t5 Figure 15: IOR# Timing (Non-68000) Table 7-6: IOR# Timing (Non-68000) Symbol t1 t2 t3 t4 t5 Parameter AB[9:0], BHE# and IOCS# valid before IOR# falling edge AB[9:0], BHE# and IOCS# hold from IOR# rising edge IOR# falling edge to DB[15:0] valid DB[15:0] hold from IOR# rising edge IOR# rising edge to DB[15:0] hi-z delay Min 10 20 80 25 30 3V/3.3V Typ Max Min 0 10 60 20 30 5V Typ Max Units ns ns ns ns ns Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 34 Epson Research and Development Vancouver Design Center MEMW# Timing AB[19:0] BHE# t1 MEMCS# t2 MEMW# t3 READY Hi-Z t6 Hi-Z t5 DB[15:0] t4 Hi-Z VALID Hi-Z VALID Figure 16: MEMW# Timing (Non-68000) Table 7-7: MEMW# Timing (Non-68000) 3V/3.3V Symbol t1 t2 t3 t4 t5 t6 Parameter AB[19:0], BHE# and MEMCS# valid before MEMW# falling edge AB[19:0], BHE# and MEMCS# hold from MEMW# rising edge MEMW# falling edge to READY falling edge MEMW# falling edge to DB[15:0] valid DB[15:0] hold from MEMW# rising edge READY negated pulse width 0 3.5* MCLK + 20 Min 0 0 30 120 0 3.5* MCLK + 10 Typ Max Min 0 0 20 140 5V Typ Max Unit s ns ns ns ns ns ns Where MCLK period = 1/fOSC, or 2/fOSC, or 4/fOSC depending on which mode the chip is in. (see section 9.2 and 9.3). SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 35 MEMR# Timing AB[19:0] BHE# t1 MEMCS# VALID t2 MEMR# t3 READY Hi-Z t7 Hi-Z t6 t5 DB[15:0] Hi-Z t4 VALID Hi-Z Figure 17: MEMR# Timing (Non-68000) Table 7-8: MEMR# Timing (Non-68000) Symbol t1 t2 t3 t4 t5 t6 t7 Parameter AB[19:0], BHE# and MEMCS# valid before MEMR# falling edge AB[19:0], BHE# and MEMCS# hold from MEMR# rising edge MEMR# falling edge to READY falling edge READY rising edge to DB[15:0] valid DB[15:0] hold from MEMR# rising edge MEMR# rising edge to DB[15:0] hi-z delay READY negated pulse width 3V/3.3V Min Typ Max 0 0 30 15 30 30 3.5* MCLK + 30 Min 0 0 20 10 28 30 3.5* MCLK + 10 5V Typ Max Units ns ns ns ns ns ns ns Where MCLK period = 1/fOSC, or 2/fOSC, or 4/fOSC depending on which mode the chip is in. (see section 9.2 and 9.3) Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 36 Epson Research and Development Vancouver Design Center 7.2 Clock Input Requirements Clock Input Waveform tPWH 90% V IH V IL tPWL 10% tr TOSC tf Figure 18: Clock Input Requirements Table 7-9: Clock Input Requirements Symbol TOSC tPWH tPWL tf tr Parameter Input Clock Period (CLKI) Input Clock Pulse Width High (CLKI) Input Clock Pulse Width Low (CLKI) Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) Min 40 40 40 5 5 60 60 Typ Max Units ns TOSC TOSC ns ns 7.2.1 Recommended Clock Input The nominal frequency must be calculated based on the formulas found in Frame Rate Calculation on page 61. The crystal oscillator must be "fundamental mode" and have the following recommended RC load values: RL = 2M 5% CL = 6.8 pF The figure below demonstrates both a crystal interface and an oscillator interface to the SED1352. . Crystal Interface 92 CL Oscillator Interface VCC 92 OUT VCC SED1352 RL X1 SED1352 GND NC X1 93 CL 93 Figure 19: Recommended Clock Interface SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 37 7.3 Display Memory Interface Timing 7.3.1 Write Data to Display Memory VA[15:0] VSC0#, VSC1# VALID t1 VWE# t2 t4 t3 VOE# t5 Hi-Z Hi-Z t6 Hi-Z Hi-Z VD[15:0] INPUT OUTPUT INPUT Figure 20: Write Data to Display Memory Table 7-10: Write Data to Display Memory Symbol t1 t2 t3 t4 t5 t6 Parameter Address cycle time VA[15:0], VCS0# and VCS1# valid before VWE# falling edge VA[15:0], VCS0# and VCS1# hold from VWE# rising edge Pulse width of VWE# VD[15:0] setup to VWE# rising edge VD[15:0] hold from VWE# rising edge Min 3V/3.3V Typ Max Min MCLK 10 MCLK/2 10 0 MCLK/2 5 MCLK/2 20 0 5V Typ Max Units ns ns ns ns ns ns MCLK - 10 MCLK/2 20 0 MCLK/2 - 5 MCLK/2 20 0 Where MCLK period = 1/fOSC, or 2/fOSC, or 4/fOSC depending on which mode the chip is in. (see section 9.2 and 9.3). Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 38 Epson Research and Development Vancouver Design Center 7.3.2 Read Data From Display Memory VA[15:0] VSC0#, VSC1# VALID t1 t2 VD[15:0] INPUT INPUT t3 INPUT Figure 21: Read Data From Display Memory Table 7-11: Read Data From Display Memory Symbol t1 t2 t3 Parameter Address cycle time VA[15:0], VCS0# and VCS1# access time VD[15:0] hold time 0 Min MCLK 10 3V/3.3V Typ Max Min MCLK 10 5V Typ Max MCLK 50 0 MCLK 30 Where MCLK period = 1/fOSC, or 2/fOSC, or 4/fOSC depending on which mode the chip is in. (See sections 9.2 and 9.3.) SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 39 7.4 LCD Interface Timing SED1352 outputs t2 YD t3 t1 LP t4 WF SED1352 outputs (AUX[01h] bit 5 = 0) LP t8 t5 t6 t7a t9 t10 XSCL t11 UD[3:0] LD[3:0] t12 1 2 SED1352 outputs (AUX[01h] bit 5 = 1) LP t7b t6b, t6c t13 t9 t8 t10 XSCL t11 t12 UD[3:0] LD[3:0] 80 1 2 Figure 22: LCD Interface Timing Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 40 Epson Research and Development Vancouver Design Center 7.4.1 4-Bit Single LCD Interface Timing Table 7-12: 4-Bit Single LCD Interface Timing Symbol t1 t2a t2b t3a t3b t4 t5 t6a t6b t7a t7b t8 t9 t10 t11 t12 t13a t13b LP period YD hold from LP negated (R1 bit 5 = 0) YD hold from LP negated (R1 bit 5 = 1) LP pulse width (R1 bit 5 = 0) LP pulse width (R1 bit 5 = 1) WF delay from LP falling edge LP setup to XSCL falling edge (R1 bit 5 = 0) LP hold from XSCL falling edge (R1 bit 5 = 0) LP negated to XSCL falling edge (R1 bit 5 = 0) LP negated to XSCL falling edge (R1 bit 5 = 1) XSCL period XSCL high width XSCL low width UD[3:0] setup to XSCL falling edge UD[3:0] hold from XSCL falling edge LP negated to XSCL rising edge (R1 bit 5 = 0) LP negated to XSCL rising edge (R1 bit 5 = 1) Parameter Min HT - 24 8tOSC - 24 13tOSC - 24 6tOSC - 24 5tOSC - 24 0 2tOSC - 24 2tOSC - 24 2tOSC - 24 7tOSC - 24 4tOSC - 24 2tOSC - 24 2tOSC - 24 2tOSC - 24 2tOSC - 24 0 5tOSC - 24 20 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns XSCL falling edge to LP falling edge (R1 bit 5 = 1 only) 13tOSC - 24 Where HT = (number of horizontal panel pixels + 16 ) * tOSC , where tOSC = 1/fOSC. SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 41 7.4.2 8-Bit LCD Interface Timing Table 7-13: 8-Bit LCD Interface Timing Symbol t1a t1b t2a t2b t3a t3b t4 t5 t6a t6b t6c t7a t7b t8 t9 t10 t11 t12 t13a t13b Parameter LP period (single panel mode) LP period (dual panel mode) YD hold from LP negated (R1 bit 5 = 0) YD hold from LP negated (R1 bit 5 = 1) LP pulse width (R1 bit 5 = 0) LP pulse width (R1 bit 5 = 1) WF delay from LP falling edge LP setup to XSCL falling edge (R1 bit 5 = 0) LP hold from XSCL falling edge (R1 bit 5 = 0) XSCL falling edge to LP falling edge - single panel mode (R1 bit 5 = 1 only) Min HT - 24 2*HT - 24 8tOSC - 24 13tOSC - 24 6tOSC - 24 5tOSC - 24 0 2tOSC - 24 4tOSC - 24 15tOSC - 24 20 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns XSCL falling edge to LP falling edge - dual panel mode 31tOSC - 24 (R1 bit 5 = 1 only) LP negated to XSCL falling edge (R1 bit 5 = 0) LP negated to XSCL falling edge (R1 bit 5 = 1) XSCL period XSCL high width XSCL low width UD[3:0], LD[3:0] setup to XSCL falling edge UD[3:0], LD[3:0] hold from XSCL falling edge LP negated to XSCL rising edge (R1 bit 5 = 0) LP negated to XSCL rising edge (R1 bit 5 = 1) 4tOSC - 24 9tOSC - 24 8tOSC - 24 4tOSC - 24 4tOSC - 24 4tOSC - 24 4tOSC - 24 0 5tOSC - 24 Where HT = (number of horizontal panel pixels + 16 ) * tOSC , where tOSC = 1/fOSC. Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 42 Epson Research and Development Vancouver Design Center LCD Interface Pixel/Data Position UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Panel - Top 8-bit Single Panel LD3 LD2 LD1 LD0 Dual Panel - Bottom UD3 UD2 UD1 UD0 4-bit Single Panel Figure 23: LCD Interface Pixel/Data Position SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 43 LP : 2 4 0 P ULS E S LP: 4 PULSES YD LP WF U D [3 :0 ] LINE 1 LINE 2 LINE 3 LINE 4 LINE 23 9 LINE 2 40 LINE 1 LINE 2 LP WF XSCL: 80 CLOCK PERIODS XS C L UD3 1-1 1 -2 1-5 1-6 1-7 1 -8 1 -317 1 -318 1 -319 UD2 UD1 UD0 1-3 1 -4 1-320 Example Timing for a 320x240 single panel Figure 24: 4-Bit Single Monochrome Panel Timing Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 44 Epson Research and Development Vancouver Design Center LP : 4 8 0 P U LS E S LP: 4 PULSES YD LP WF U D [3 :0 ], LD [3 :0 ] LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 LP WF XSCL:80 CLOCK PERIODS XS C L UD3 UD2 UD1 UD0 LD 3 LD2 LD1 LD 0 Example timing for a 640x480 panel 1-1 1-2 1-3 1-4 1-5 1-9 1 -10 1 -6 33 1-634 1-63 5 1-11 1-12 1-13 1-636 1-63 7 1-63 8 1-63 9 1-64 0 1-6 1-7 1-14 1 -15 1-8 1-16 Figure 25: 8-Bit Single Monochrome Panel Timing SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 45 LP : 2 4 0 P U LS E S LP: 2 PULSES YD LP WF U D [3 :0 ], LD [3 :0 ] LINE 1/24 1 LINE 2/24 2 LINE 3/243 LINE 4/24 4 LINE 2 39/4 79 LINE 24 0/48 0 LINE 1 /2 4 1 LINE 2/24 2 LP WF XSCL: 160 CLOCK PERIODS XS C L UD3 UD2 UD1 UD0 LD 3 LD2 LD1 LD 0 1 -1 1 -2 1 -5 1-637 1-6 1-638 1-639 1-3 1-4 241-1 1-7 1-8 241 -5 1-640 241-637 241-638 241-639 241-640 241-2 2 4 1 -3 2 4 1 -4 241-6 2 4 1-7 2 4 1-8 Example timing for a 640x480 panel Figure 26: 8-Bit Dual Monochrome Panel Timing Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 46 Epson Research and Development Vancouver Design Center 8 HARDWARE REGISTER INTERFACE The SED1352 is configured and controlled via 15 internal 8-bit registers. There are two ways to map these registers into the system I/O space. 1. Direct-mapping: Absolute I/O address = system address lines AB[3:0] + base I/O mapped address (where base I/O address is selected by VD7-VD12, see Table 5-6) This scheme requires 16 sequential I/O addresses starting from the I/O mapped base address selected by VD7-VD12 (see Table 5-6). To perform an I/O access: write data IOW {absolute I/O address}, {data} read data IOR {absolute I/O address} 2. Indexing: I/O address = internal index register bits [3:0] This scheme requires 2 sequential I/O addresses starting from the base address selected by VD4-VD12 (see Table 5-6). To perform an 8-bit I/O access: write index IOW {I/O mapped address}, {index} then write data IOW {I/O mapped address +1}, {data} or read data IOR {I/O mapped address +1} ; write the index of the register to be accessed ; write data to the indexed register ; read the indexed register To perform a 16-bit I/O access: write data IOW {I/O mapped address}, {index, data} ; write the index and data of the register to be accessed read data IOW {I/O mapped address}, {index} IOR {I/O mapped address +1} ; write to the indexed register ; read the indexed register Note Bits marked "n/o" should be set to 0 in the following registers. 8.1 Register Descriptions AUX[00h] Test Register I/O address = 0000b, Read/Write Test Mode Enable bit 7 Reserved Test Input Select Bit 2 Test Input Select Bit 1 Test Input Select Bit 0 Test Output Select Bit 2 Test Output Select Bit 1 Test Output Select Bit 0 Test Mode Enable When this bit = 0 normal operation is enabled. When this bit = 1 the chip is placed in a special test mode. The test input bits and test output bits (bits 6:0) are used to select various internal test functions. Reserved During normal operation this bit must = 0. Test Mode Input Bits [2:0] and Output Bits [2:0] When bit 7 = 1 these are the Test Input Select Input and Output bits. When bits 6 and 7 = 0 (normal operation) these bits may be used as read/write scratch registers. bit 6 bits 5-0 SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 47 AUX[01h] Mode Register I/O address = 0001b, Read/Write. DISP bit 7 Panel Mask XSCL LCDE Gray Scale LCD Data Width Memory Interface RAMS DISP This bit selects display on or off. When this bit = 0, Display OFF is selected (LD0-3 and UD0-3 are forced to 0). When this bit = 1, Display ON is selected. This bit goes low on RESET. Panel This bit selects the LCD panel configuration (single or dual). When this bit = 0, Single LCD panel drive is selected. When this bit = 1 Dual LCD panel drive is selected. This bit goes low on RESET. Mask XSCL When this bit = 0 XSCL is not masked off during the horizontal non-display period. When this bit = 1 XSCL is masked off during the horizontal non-display period. This bit goes low on RESET. LCDE The state of this pin determines the state of output pin 82, LCDENB, and is intended for control of an external LCDBIAS power supply. However, this pin can be used as a General I/O pin if desired. When LCDE = 0, LCDENB is forced low. When LCDE = 1, LCDENB is forced high. This bit goes low on RESET. Gray Scale Selects between 16-level or 4-level gray scale display. When this bit = 1, 16 gray shades are displayed (4 bits/pixel). When this bit = 0, 4 gray shades are displayed (2 bits/pixel). This bit goes low on RESET. LCD Data Width Selects between 4-bit and 8-bit display data widths for single LCD mode. When this bit = 1, 8-bit data transfer width is enabled. When this bit = 0, 4-bit data transfer width is enabled. In dual panel mode the data transfer width is forced to 4 bits per panel. This bit goes low on RESET. Memory Interface This bit selects between the 8-bit or 16-bit memory interface. When this bit = 0, the 16-bit memory interface is selected. When this bit = 1, the 8-bit memory interface is selected. If 16-bit bus interface is selected (VD0 = 1 on RESET), the Memory Interface bit is forced to 0 internally (16-bit). This bit goes low on RESET. RAMS This bit configures the display memory address lines for an 8-bit memory interface system. When this bit = 0, addressing for 8Kx8 SRAM on an 8-bit display memory data bus interface is selected. When this bit = 1, addressing for 32Kx8 SRAM on an 8-bit display memory data bus interface is selected. This bit goes low on RESET. This bit is ignored for a 16-bit memory interface. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 48 Epson Research and Development Vancouver Design Center AUX[02h] Line Byte Count Register (LSB) I/O address = 0010b, Read/Write. Line Byte Count Bit 7 bits 7-0 Line Byte Count Bit 6 Line Byte Count Bit 5 Line Byte Count Bit 4 Line Byte Count Bit 3 Line Byte Count Bit 2 Line Byte Count Bit 1 Line Byte Count Bit 0 Line Byte Count Bits [7:0] These are the 8 LSB of the 9 bit Total Display Line Count and represent the number of scan lines -1, to a maximum value of 3FFh or 1024 scan lines. Line Byte Count Bit 8 is located in register AUX[05h] and is ignored in the 16-bit memory interface. To calculate the Line Byte Count use the following formula: BitsPerPixel LineByteCount = ------------------------------------------------------------- x HorizontalResolution - 1 MemoryInterfaceWidth Example: To calculate the Line Byte Count for 640 horizontal pixels with 16 gray shades (4 bits-per-pixel) and 16-bit memory interface: 4BitsPerPixel LineByteCount = ------------------------------------ x 640 - 1 = 159 16Bits The following two tables summarize the maximum value of the Line Byte Count Register for different display modes and display memory interface. Table 8-1: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface Display Mode 4-level gray shades 16-level gray shades Maximum Value of Line Byte Count Register 0FFh 1FFh Corresponding Maximum Number of Pixels in One Display Line 256 x 4 = 1024 512 x 2 = 1024 Table 8-2: Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface Display Mode 4-level gray shades 16-level gray shades Maximum Value of Line Byte Count Register 0FFh 0FFh Corresponding Maximum Number of Pixels in One Display Line 256 x 8 = 2048 256 x 4 = 1024 AUX[03h] Line Byte Count Power Save Register (MSB) I/O address = 0011b, Read/Write PS Bit 1 bits 7-6 PS Bit 0 LCD Signal LUT State Bypass n/a n/a n/a Line Byte Count Bit 8 PS Bits [1:0] Selects the Power Save Modes as shown in the following table. The PS bits [1:0] go low on RESET. SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 49 Table 8-3: Power Save Mode Selection PS1 0 0 1 1 PS0 0 1 0 1 Mode Activated Normal Operation Power Save Mode 1 Power Save Mode 2 Reserved Refer to Power Save Modes (PSM 1) on page 55 for a complete Power Save Mode description. bit 5 LCD Signal State When this bit = 0, all LCD interface signals are forced low during Power Save modes. When this bit = 1, all LCD interface signals are forced to a high impedance (Hi-Z) state during Power Save modes. This bit goes low on RESET. LUT Bypass When the LUT Bypass bit = 0 the Look-Up Table is used for display data output. When this bit = 1, the Look-Up Table is bypassed for display data output (for power save purposes). The LUT Bypass bit goes low on RESET. Line Byte Count Bit 8 This is the MSB of the number of bytes to be fetched per display line minus 1 (see AUX[02h]). This bit only has effect when in 16 gray shades with 8-bit memory interface. This bit is ignored in the 16-bit memory interface. bit 4 bit 0 . AUX[04h] Total Display Line Count Register (LSB) (Vertical Total) I/O address = 0100b, Read/Write. Total Display Line Count Bit 7 bits 7-0 Total Display Line Count Bit 6 Total Display Line Count Bit 5 Total Display Line Count Bit 4 Total Display Line Count Bit 3 Total Display Line Count Bit 2 Total Display Line Count Bit 1 Total Display Line Count Bit 0 Total Display Line Count Bits [7:0] These are the 8 LSB of the 10 bit Total Display Line Count and represent the number of scan lines -1, to a maximum value of 3FFh or 1024 scan lines. In single panel mode: TotalDisplayLineCount = NumberOfDisplayLines - 1 In dual panel mode: NumberOfDisplayLines TotalDisplayLineCount = -------------------------------------------------------------- - 1 2 Note Note that the value programmed partially determines the frame period, and hence affects display duty cycle. Bits 8 and 9 are located in the following register (AUX[05h]). Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 50 Epson Research and Development Vancouver Design Center AUX[05h] Total Display Line Count Register (MSB) and WF Count Register I/O address = 0101b, Read/Write WF Count Bit 5 WF Count Bit 4 WF Count Bit 3 WF Count Bit 2 WF Count Bit 1 WF Count Bit 0 Total Display Line Count Bit 9 Total Display Line Count Bit 8 bits 7-2 WF Count Bits [5:0] These bits are used to adjust the WF output signal period. The binary value stored in these bits represents the number of LP pulses -1 between toggles of the WF output. The power up reset value of these bits is 0, which causes the WF output to toggle every frame. When values of 01h to 3Fh are programmed into these bits, the results are WF toggling every 1+n LP pulses, where n is the value programmed. Total Display Line Count Bits [9:8] These are the two MSB of the Total Display Line Count Register, AUX[04h]. bits 1-0 AUX[06h] Screen 1 Display Start Address Register (LSB) I/O address = 0110b, Read/Write. Screen 1 Display Start Addr Bit 7 Screen 1 Display Start Addr Bit 6 Screen 1 Display Start Addr Bit 5 Screen 1 Display Start Addr Bit 4 Screen 1 Display Start Addr Bit 3 Screen 1 Display Start Addr Bit 2 Screen 1 Display Start Addr Bit 1 Screen 1 Display Start Addr Bit 0 AUX[07h] Screen 1 Display Start Address Register (MSB) I/O address = 0111b, Read/Write. Screen 1 Display Start Addr Bit 15 Screen 1 Display Start Addr Bit 14 Screen 1 Display Start Addr Bit 13 Screen 1 Display Start Addr Bit 12 Screen 1 Display Start Addr Bit 11 Screen 1 Display Start Addr Bit 10 Screen 1 Display Start Addr Bit 9 Screen 1 Display Start Addr Bit 8 AUX[06h] bits 7-0 Screen 1 Display Start Address Bits [15:0] AUX[07h] bits 7-0 These 16 bits determine the Screen 1 Display Start Address. In an 8-bit memory configuration these bits set the 16-bit start address (i.e., byte access). In a 16-bit memory configuration these are the 16 most significant bits of a 17-bit start address (i.e., word access). The Screen 1 Display Start Address is the memory address corresponding to the first displayed pixel (top left corner). In a dual panel configuration, screen 1 refers to the upper half of the display. While in a single panel configuration, screen 1 refers to the first screen of the Split Screen Display feature where two different images (screen 1 and screen 2) can be displayed at the same time on one display. Note The absolute address into display memory is determined by the Memory Mapping Address which is set by VD13 - VD15 (see Table 5-6, "Summary of Power On / Reset Options," on page 25). SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 51 AUX[08h] Screen 2 Display Start Address Register (LSB) I/O address = 1000b, Read/Write. Screen 2 Display Start Addr Bit 7 Screen 2 Display Start Addr Bit 6 Screen 2 Display Start Addr Bit 5 Screen 2 Display Start Addr Bit 4 Screen 2 Display Start Addr Bit 3 Screen 2 Display Start Addr Bit 2 Screen 2 Display Start Addr Bit 1 Screen 2 Display Start Addr Bit 0 AUX[09h] Screen 2 Display Start Address Register (MSB) I/O address = 1001b, Read/Write. Screen 2 Display Start Addr Bit 15 Screen 2 Display Start Addr Bit 14 Screen 2 Display Start Addr Bit 13 Screen 2 Display Start Addr Bit 12 Screen 2 Display Start Addr Bit 11 Screen 2 Display Start Addr Bit 10 Screen 2 Display Start Addr Bit 9 Screen 2 Display Start Addr Bit 8 AUX[08h] bits 7-0 Screen 2 Display Start Address Bits [15:0] AUX[09h] bits 7-0 These 16 bits determine the Screen 2 Display Start Address. In an 8-bit memory configuration these bits set the 16-bit start address (i.e., byte access). In a 16-bit memory configuration these are the 16 most significant bits of a 17-bit start address (i.e., word access). In a dual panel configuration, screen 2 refers to the lower half of the display. The Screen 2 Display Start Address is the memory address corresponding to first displayed pixel in the first line of the lower half of the display. If screen 2 is started right after screen 1, the Screen 2 Display Start Address is calculated with the following formula. Screen2DisplayStartAddress ( hex ) = ( ImageHorizontalResolution ) x ( ImageVerticalResolution ) x ( BytesPerPixel ) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Screen1DisplayStartAddress MemoryInterfaceWidth 2 x ---------------------------------------------------------------- 8 In a single panel configuration, screen 2 refers to the second screen of the Split Screen Display Feature where two different images (screen 1 and screen 2) can be displayed at the same time on one display. The Screen 2 Display Start Address is the memory address corresponding to the first pixel of the second image stored in display memory. To display screen 2 refer to AUX[0Ah] Screen 1 Display Line Count Register (LSB) below. Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 52 Epson Research and Development Vancouver Design Center AUX[0Ah] Screen 1 Display Line Count Register (LSB) I/O address = 1010b, Read/Write. Screen 1 Display Line Count Bit 7 Screen 1 Display Line Count Bit 6 Screen 1 Display Line Count Bit 5 Screen 1 Display Line Count Bit 4 Screen 1 Display Line Count Bit 3 Screen 1 Display Line Count Bit 2 Screen 1 Display Line Count Bit 1 Screen 1 Display Line Count Bit 0 AUX[0Bh] Screen 1 Display Line Count Register (MSB) I/O address = 1011b, Read/Write. Screen 1 Display Line Count Bit 9 Screen 1 Display Line Count Bit 8 n/a n/a n/a n/a n/a n/a AUX[0Ah] bits 7-0Screen 1 Display Line Count Bits [9:0] AUX[0Bh] bits 1-0 These bits are the eight LSB of a 10-bit value used to determine the number of lines displayed for screen 1. The remaining lines will automatically display from the Screen 2 Display Start Address. The 10-bit value programmed is the number of display lines -1. This register is used to enable the split screen display feature (single panel only) where two different images can be displayed at the same time on one display. For example; AUX[0Ah] = 20h for a 320x240 display system. The display will display 20h+1 = 33 lines on the upper part of the screen as dictated by the Screen 1 Display Start Address Registers (AUX[06h] and AUX[07h]), and 240 - 33 = 207 lines will be displayed on the lower part of the screen as dictated by the Screen 2 Display Start Address Registers (AUX[08h] and AUX[09h]). Two different images can be displayed when using a dual panel configuration by changing the Screen 2 Display Start Address. However, by using this method screen 2 is limited to the lower half of the display. This register is ignored in dual panel mode. AUX[0Dh] Address Pitch Adjustment Register I/O address = 1101b, Read/Write. Addr Pitch Adjustment Bit 7 bits 7-0 Addr Pitch Adjustment Bit 6 Addr Pitch Adjustment Bit 5 Addr Pitch Adjustment Bit 4 Addr Pitch Adjustment Bit 3 Addr Pitch Adjustment Bit 2 Addr Pitch Adjustment Bit 1 Addr Pitch Adjustment Bit 0 Addr Pitch Adjustment Bits [7:0] These bits set the numerical difference between the last address of a display line, and the first address in the following line. If the Address Pitch Adjustment is not equal to zero, then a virtual screen is formed. The size of the virtual screen is only limited by the available display memory. The actual display output is a window that is part of the whole image stored in the display memory. For example, with 128K of display memory, a 640x400 16-gray image can be stored. If the output display size is 320x240, then the whole image can be seen by changing display starting addresses through AUX[06h] and [07h], and AUX[08h] and [09h]. Note that a virtual screen can be produced on either a single or dual panel. SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 53 In 8-bit memory interface, if the Address Pitch Adjustment is not equal to zero, then a virtual screen with a line length of (Line Byte Count +AUX[0Dh]+1) bytes is created, with the display reflecting the contents of a window (Line Byte Count+1) bytes wide. The position of the window on the virtual screen is determined by AUX[06h] and [07h], and AUX[08h] and [09h]. In 16-bit memory interface, if the Address Pitch Adjustment is not equal to zero, then a virtual screen with a line length of 2(Line Byte Count +AUX[0Dh]+1) bytes is created, with the display reflecting the contents of a window 2(Line Byte Count+1) bytes wide. The position of the window on the virtual screen is determined by AUX[06h] and [07h], and AUX[08h] and [09h]. . AUX[0Eh] Look-Up Table Address Register I/O address = 1110b, Read/Write Bank Bit 1 Bank Bit 0 Palette ID Bit ID Bit Address (Read Only) (Read Only) Bit 3 Palette Address Bit 2 Palette Address Bit 1 Palette Address Bit 0 The SED1352 has one internal 16 position, 4-bit wide Look-Up Table (palette). The 4-bit value programmed into each table position determines the output gray shade/weighting of display data. The Look-Up Table can be arranged in two different configurations. Refer to Table 27, "4-Level Gray-Shade Mode LookUp Table Architecture," on page 54 for formats. bits 7-6 Bank Bits [1:0] In 4-level gray mode (2-bits/pixel), the 16 position palette is arranged into four, 4 position "banks". These two bits control which bank is currently selected. These bits have no effect in 16-level gray mode (4bits/pixel). ID Bits After power on or hardware reset, these bits can be read to identify the current revision of the SED1352. These same bits are used to identify the pin compatible SED1352F0x and would only be used in system implementations where common software is utilized. As these bits are R/W they must be read before being written in order to be used as ID bits. Table 8-4: ID Bit Usage Chip Power On or RESET SED1353 F352 SED1352F0B/F1B/D0B SED1352F0A Aux[0Eh] bit 5 0 0 1 1 bit 4 0 1 0 1 bits 5-4 bits 3-0 Palette Address Bits [3:0] These 4 bits provide a pointer into the 16 position Look-Up Table currently selected for CPU R/W access. Note The Look-Up Table configuration (e.g. 1/2 banks) does not affect the R/W access from the CPU as all 16 positions can be accessed sequentially. Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 54 Epson Research and Development Vancouver Design Center AUX[0Fh] Look-Up Table Data Register I/O address = 1111b, Read/Write. n/a bits 3-0 n/a n/a n/a Palette Data Palette Data Palette Data Palette Data Bit 3 Bit 2 Bit 1 Bit 0 Palette Data Bits [3:0] These 4-bits are the gray shade values used for display data output. They are programmed into the 4-bit Look-Up Table (palettes) positions pointed to by Palette Address bits [3:0]. For example: in a 16-level gray shade display mode, a data value of 0001b (4-bits / pixel) will point to Look-Up Table position one and display the 4-bit gray shade corresponding to the value programmed into that location. 8.2 Look-Up Table Architecture 8.2.1 4-Level Gray Shade Mode Look-Up Table Bank 0 2 bit pixel data 0 1 2 3 Bank 1 0 1 2 3 Bank 2 0 1 2 3 Bank Select Logic 4-bit display data output Bank 3 0 1 2 3 Bank Select bits [1:0] (Aux[0Eh] bits [7:6]) Note: the above depiction is intended to show the display data output path only. The CPU R/W access to the individual Look-Up Tables is not affected by the various `banking' configurations. Figure 27: 4-Level Gray-Shade Mode Look-Up Table Architecture SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 55 8.2.2 16-Level Gray Shade Mode Look-Up Table 16x4 0 1 2 3 C D E F 4 bit pixel data ( P3, P2, P1, P0 ) msb lsb 4 bit Look-Up Table data output Figure 28: 16-Level Gray-Shade Mode Look-Up Table Architecture 8.3 Power Save Modes (PSM 1) Two software-controlled Power Save Modes have been incorporated into the SED1352 to accommodate the important need for power reduction in the hand-held devices market. These modes can be enabled by setting the 2 Power Save bits (AUX[03h] bits 7-6). The various settings are: Table 8-5: Power Save Mode Selection Bit 7 Bit 6 0 0 0 1 1 0 1 1 Mode Activated Normal Operation Power Save Mode 1 Power Save Mode 2 Reserved 8.3.1 Power Save Mode 1 (PSM1) Power Save Mode 1 has two states. Initially when set, the SED1352 enters State 1. If no valid memory cycle is detected within 1, 2, or 4 clocks (input clock frequency dependent), the chip will enter State 2. The number of clocks of inactivity before entering State 2 is dependent on the display memory interface and the number of gray shades. State 1 * * * I/O read/write of all registers allowed Memory read/write allowed LCD outputs are either forced low (AUX[03h] bit 5=0), or high impedance (AUX[03h] bit 5=1) State 2 The same as State 1 as well as: * Master clock for display memory access is disabled Once a valid memory read/write cycle is detected, the SED1352 returns to State 1 where the MPU access is serviced. The transition from going from State 2 to State 1 requires 1, 2, or 4 clocks (as described above). Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 56 Epson Research and Development Vancouver Design Center 8.3.2 Power Save Mode 2 (PSM2) * * * * * I/O read/write of all registers allowed Memory read/write is disabled Master clock for display memory access is disabled LCD outputs are either forced low (AUX[03h] bit 5=0), or high impedance (AUX[03h] bit 5=1) Internal oscillator is disabled. 8.3.3 Power Save Mode Function Summary Table 8-6: Power Save Mode Function Summary Function Display Active? I/O Access Possible? Memory Access Possible? Sequence Controller Running? Internal Oscillator Disabled? Normal (Active) Yes Yes Yes Yes No Power Save Mode (PSM) PSM1 State 1 State 2 No No Yes Yes Yes No No No No No PSM2 No Yes No No Yes 8.3.4 Pin States in Power Save Modes Table 8-7: Pin States in Power Save Modes Pin UD[3:0], LD[3:0], LP, XSCL, YD, WF (Note 1) UD[3:0], LD[3:0], LP, XSCL, YD, WF (Note 2) AB[19:0], DB[15:0] IOR#, IOW# MEMR#, MEMW# RESET Normal (Active) Active Pin State PSM1 State 1 State 2 High Impedance High Impedance PSM2 High Impedance Active Active Active Active Active Forced Low Forced Low Forced Low Active Active Active Active Active Active Active Active Active Active Active Active Note Internal Register AUX[03h], bit 5 = 1. Internal Register AUX[03h], bit 5 = 0. SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 57 9 DISPLAY MEMORY INTERFACE 9.1 SRAM Configurations Supported 9.1.1 8-Bit Mode VD0-7 VWE# WE# SED1352 8Kx8 CS# VCS0# VCS1# VA0-12 n/c Figure 29: 8-Bit Mode - 8K bytes SRAM VD0-7 VWE# WE# WE# SED1352 8Kx8 CS# 8Kx8 CS# VCS0# VCS1# VA0-12 Figure 30: 8-Bit Mode - 16K bytes SRAM (Requires AUX[01h] bit 0 = 0) Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 58 Epson Research and Development Vancouver Design Center VD0-7 VWE# WE# SED1352 32Kx8 CS# VCS0# VCS1# VA0-14 n/c Figure 31: 8-Bit Mode - 32K bytes SRAM (Requires AUX[01h] bit 0 = 1) VD0-7 VWE# WE# WE# SED1352 8K/32Kx8 CS# 32K/8Kx8 CS# VCS0# VCS1# VA0-14 Figure 32: 8-Bit Mode - 40K bytes SRAM [either (8Kx8 + 32Kx8) requiring AUX[01h] bit 0 = 0 or (32Kx8 + 8Kx8) requiring AUX[01h] bit 0 = 1] SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 59 VD0-7 VWE# WE# WE# SED1352 32Kx8 CS# 32Kx8 CS# VCS0# VCS1# VA0-14 Figure 33: 8-Bit Mode - 64K bytes SRAM (Requires AUX[01h] bit 0 = 1) 9.1.2 16-Bit Mode VD0-7 VWE# WE# SED1352 VCS0# VA0-12 VCS1# 8Kx8 CS# CS# 8Kx8 WE# VD8-15 Figure 34: 16-Bit Mode - 16K bytes SRAM Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 60 Epson Research and Development Vancouver Design Center VD0-7 VWE# WE# SED1352 VCS0# VA0-14 VCS1# 32Kx8 CS# CS# 32Kx8 WE# VD8-15 Figure 35: 16-Bit Mode - 64K bytes SRAM VWE# WE# SED1352 VCS0# VCS1# LB# UB# 64Kx16 VA0-15 VD0-7 VD8-15 A0-15 I/O 1-8 I/O 9-16 Figure 36: 16-Bit Mode - 128K bytes SRAM SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 61 9.2 SRAM Access Time 9.2.1 8-Bit Display Memory Interface: Table 9-1: 8-Bit Display Memory Interface SRAM Access Time Display Mode 16-level gray shades 4-level gray shades 3V/3.3V Access time < 1 / fOSC - 50ns Access time < 2 / fOSC - 50ns 5V Access time < 1 / fOSC - 30ns Access time < 2 / fOSC - 30ns 9.2.2 16-Bit Display Memory Interface: Table 9-2: 16-Bit Display Memory Interface SRAM Access Time Display Mode 16-level gray shades 4-level gray shades 3V/3.3V Access time < 2 / fOSC - 50ns Access time < 4 / fOSC - 50ns 5V Access time < 2 / fOSC - 30ns Access time < 4 / fOSC - 30ns 9.3 Frame Rate Calculation 9.3.1 For Single Panel : fosc FrameRate = --------------------------------------------------------------------------------------------------------------------------------------( HorizontalPixels + DHNDP ) x ( VerticalLines + 4 ) 9.3.2 For Dual Panel : fosc FrameRate = ------------------------------------------------------------------------------------------------------------------------------------------------VerticalLines ( HorizontalPixels + DHNDP ) x 2 x ----------------------------------- + 2 2 Where DHNDP is Default Horizontal Non-Display Period in term of pixels: DHNDP = 16 pixels per panel. 9.4 Memory Size Calculation Memory Size (bytes) = ( HorizontalPixels ) x ( VerticalLines ) x ( BitsPerPixel ) ----------------------------------------------------------------------------------------------------------------------------------------------8 Example: For a 640x480, 4 gray shades (2 bits-per-pixel) system: Memory Size (bytes) = ( 640 ) x ( 480 ) x ( 2 ) ----------------------------------------------- = 76800bytes = 75Kbyte 8 Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 62 Epson Research and Development Vancouver Design Center 9.5 Memory Size Requirement The following tables summarize the preceding information (formulae). Input clock (fOSC) is limited by SRAM access time depending on the display mode and display memory interface that is being used. As a result, different resolutions will have different input clock and memory requirements for a particular frame rate. Tables 9-3 through 9-5 summarize the minimum memory size and access time requirements for various resolutions at a particular input clock along with the corresponding frame rates. Table 9-3: Memory Size Requirement: Number of Horizontal Pixels = 640 Number of Horizontal Pixels = 640 4 Grays (2 bits-per-pixel) Display Memory Interface 480 Number of Vertical Lines 400 320 256 240 200 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 16 Grays (4 bits-per-pixel) Size (KB) 150 125 100 80 75 62.5 Example Input Clock (fOSC) 24 MHz 20 MHz 16 MHz 12 MHz 12 MHz 10 MHz Size (KB) 75 62.5 50 40 37.5 32 Access Time 3V/3.3V (2) 115 ns 50 ns 150 ns 75 ns 200 ns 115 ns 280 ns 115 ns 280 ns 150 ns 350 ns Access Time 3V/3.3V (1) (2) 50 ns (2) 75 ns (2) 115 ns (2) 115 ns 50 ns 150 ns 5V (2) 135 ns 70 ns 170 ns 95 ns 220 ns 135 ns 300 ns 135 ns 300 ns 170 ns 370 ns 5V (1) (2) 70 ns (2) 95 ns (2) 135 ns (2) 135 ns 70 ns 170 ns Frame Rate 76 Hz 75 Hz 75 Hz 70 Hz 75 Hz 75 Hz (1) Memory more than 128KB cannot be supported by SED1352. (2) Memory more than 64KB can only be supported through 16-bit display memory interface. * KB = K byte = 1024 bytes SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 Epson Research and Development Vancouver Design Center Page 63 Table 9-4: Memory Size Requirement: Number of Horizontal Pixels = 480 Number of Horizontal Pixels = 480 4 Grays (2 bits-per-pixel) Display Memory Interface 480 Number of Vertical Lines 400 320 256 240 200 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 16 Grays (4 bits-per-pixel) Size (KB) 113 94 75 60 57 47 Example Input Clock (fOSC) 18 MHz 14 MHz 12 MHz 10 MHz 8 MHz 8 MHz Size (KB) 57 47 37.5 30 29 23.5 Access Time 3V/3.3V 60 ns 170 ns 90 ns 230 ns 115 ns 280 ns 150 ns 350 ns 200 ns 450 ns 200 ns 450 ns Access Time 3V/3.3V (2) 60 ns (2) 90 ns (2) 115 ns 50 ns 150 ns 75 ns 200 ns 75 ns 200 ns 5V 80 ns 190 ns 110 ns 250 ns 135 ns 300 ns 170 ns 370 ns 220 ns 470 ns 220 ns 470 ns 5V (2) 80 ns (2) 110 ns (2) 135 ns 70 ns 170 ns 95 ns 220 ns 95 ns 220 ns Frame Rate 75 Hz 70 Hz 75 Hz 77 Hz 66 Hz 73 Hz Table 9-5: Memory Size Requirement: Number of Horizontal Pixels = 320 Number of Horizontal Pixels = 320 4 Grays (2 bits-per-pixel) Display Memory Interface 480 Number of Vertical Lines 400 320 256 240 200 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 16 Grays (4 bits-per-pixel) Size (KB) 75 62.5 50 40 37.5 32 Example Input Clock (fOSC) 12 MHz 10 MHz 8 MHz 6 MHz 6 MHz 5 MHz Size (KB) 37.5 32 25 20 19 16 Access Time 3V/3.3V 115 ns 280 ns 150 ns 350 ns 200 ns 450 ns 280 ns 615 ns 280 ns 615 ns 350 ns 750 ns Access Time 3V/3.3V (2) 115 ns 50 ns 150 ns 75 ns 200 ns 115 ns 280 ns 115 ns 280 ns 150 ns 350 ns 5V 135 ns 300 ns 170 ns 370 ns 220 ns 470 ns 300 ns 630 ns 300 ns 635 ns 370 ns 770 ns 5V (2) 135 ns 70 ns 170 ns 95 ns 220 ns 135 ns 300 ns 135 ns 300 ns 170 ns 370 ns Frame Rate 74 Hz 74 Hz 73 Hz 69 Hz 73 Hz 73 Hz (1) Memory more than 128KB cannot be supported by SED1352. (2) Memory more than 64KB can only be supported through 16-bit display memory interface. * KB = K byte = 1024 bytes Hardware Functional Specification Issue Date: 99/07/28 SED1352 X16-SP-001-16 Page 64 Epson Research and Development Vancouver Design Center 10 MECHANICAL DATA 23.2 0.04 20.0 0.1 80 51 81 50 Index 100 31 1 0.15 0.05 2.7 0.1 0.65 0.1 0.30 0.1 30 14.0 0.1 0.8 0.1 1.6 0~12 0.35 All dimensions in mm Figure 37: Mechanical Drawing QFP5-100pin-S2 SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 17.2 0.04 Epson Research and Development Vancouver Design Center Page 65 16.0 0.4 14.0 0.1 75 76 51 50 14.0 0.1 Index 100 1 0.125 0.1 1.4 0.1 0.5 25 26 0.168 0.1 0.1 0.5 0.2 1 All dimensions in mm Figure 38: Mechanical Drawing QFP15-100pin Hardware Functional Specification Issue Date: 99/07/28 16.0 0.4 0~10 SED1352 X16-SP-001-16 Page 66 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-SP-001-16 Hardware Functional Specification Issue Date: 99/07/28 SED1352 Dot Matrix Graphics LCD Controller Programming Notes and Examples Document Number: X16-BG-007-04 Copyright (c) 1996, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 2 3 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 INITIALIZING THE SED1352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 GRAY SHADES AND LOOK-UP TABLES . . . . . . . . . . . . . . . . . . . . . 15 3.1 Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 Two Bit Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.2 Four Bit Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 LUT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 Look-Up Table Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.3 Four Gray Shades (Two Bits/Pixel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4 Sixteen Gray Shades (Four Bits/Pixel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 DISPLAY MEMORY MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.1 SDU1352B0x Evaluation Board Display Memory . . . . . . . . . . . . . . . . . . . . . . 24 4.2.2 Display Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 Common Display Memory Requirements for LCD Panel Sizes . . . . . . . . . . . . . 27 5 ADVANCED TECHNIQUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 Virtual Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 5.3 Bitmaps and Text Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.1 Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.2 Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4.3 Single Panel LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4.4 Dual Panel LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.5 Panning and Scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.2 Panning Right and Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.3 Scrolling Up and Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6 Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6.2 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 4 Epson Research and Development Vancouver Design Center 6 PROGRAMMING THE SED1352 . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.1 6.2 6.3 Main Loop Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Advanced Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 5 List of Tables Table 3-1: SED1352F0B Black-To-White Look-Up Table for 16 Gray Shades . . . . . . . . . . . . . . . .17 Table 3-2: SED1352F0B Inverted Look-Up Table (White-To-Black) . . . . . . . . . . . . . . . . . . . . . 18 Table 3-3: SED1352F0B Black-To-White Look-Up Table for 4 Gray Shades . . . . . . . . . . . . . . . . .19 Table 4-1: Memory Size Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5-1: Smallest Number of Pixels for Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 5-2: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 5-3: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 5-4: Power Save Mode Function Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 List of Figures Figure 1: Pixel Storage for 2 Bits (4 Gray Shades) In One Byte of Display Memory . . . . . . . . . . . . 15 Figure 2: Pixel Storage for 4 Bits (16 gray shades) in One Byte of Display Memory . . . . . . . . . . . . 15 Figure 3: 4-Level Gray Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . 20 Figure 4: 16-Level Gray Shade Mode Look-Up Table Architecture. . . . . . . . . . . . . . . . . . . . . 21 Figure 5: Memory Map for 320 x 240 LCD Panel with 16 Gray Shades . . . . . . . . . . . . . . . . . . 25 Figure 6: Memory Map Example for 320 x 240 LCD Panel with 4 Gray Shades . . . . . . . . . . . . . . 27 Figure 7: Memory Map Example for 640 x 200 LCD Panel with 16 Gray Shades . . . . . . . . . . . . . 27 Figure 8: 640 x 480 Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 9: Font for the Message "TEXT" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 10: Display Memory Contents for Message "TEXT" . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 11: Memory Map for Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 12: 320 x 240 Single Panel for Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 13: 640 x 480 Dual Panel for Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 14: Memory Map for a Dual Panel showing a Single Image . . . . . . . . . . . . . . . . . . . . . 40 Figure 15: Display for DEMO.EXE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 7 1 INTRODUCTION The purpose of this guide is to demonstrate how to program the SED1352 LCD controller, with reference made to the SDU1352B0x evaluation board. The first half of this guide presents the basic concepts of LCD controllers, which describe the following: * * * * * * * * * Initializing the SED1352 Gray Shades and Look-Up Tables Display Memory Models Virtual Displays Bitmaps and Text Displays Registers Split Screen Panning and Scrolling Power Saving The second half of this guide presents programming examples for the following: * * * * * * * Initialization Read Registers Gray Shades and Look-Up Tables Text Split Screen Panning and Scrolling Power Saving These programming examples are combined in a simple menu-driven program. Most of the program is written in the `C' programming language, with some parts written in 8086 assembly. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 8 Epson Research and Development Vancouver Design Center 2 INITIALIZING THE SED1352 This section presents two examples to show how to initialize the SED1352 registers and write a pixel to the display. Code to initialize the SED1352 is provided in Section 6.2, "Initialization Code" on page 48. The following examples describe values written to registers. * * * A "normal" value is one which must not change after initialization of all registers. A "panel specific" value is one required for the given type of panel. Such a value must never change after initialization of all registers. An "implementation specific" value is one required for the hardware implementation of the SED1352. Such a value must never change after initialization of all registers. Refer to the SED1352F0x Hardware Functional Specification and SDU1352B0x Evaluation Board User's Manual for more information on hardware implementation issues. An "application specific" value is one that can be changed by the program after initialization of all registers. * Example 1: Initialize the registers for a 16 gray shade 320x240 single panel LCD with 64k of display memory. Afterwards write one pixel to the top left corner of the display. Program SED1352 Registers 00h-0Dh: AUX Register Data (in Binary) Notes must be zero b7 = display on (normal) b6 = single panel (panel specific) b5 = XSCL not masked (panel specific) b4 = LCDE LCDENB pin = 0 (implementation specific; the recommended procedure is to turn this bit off during register initialization and afterwards turn this bit on) b3 = 16 grays (application specific) b2 = 4 bit LCD data width (panel specific) b1 = 16 bit Memory Interface (implementation specific) b0 = RAMS ignored (implementation specific) bits 7-0 = bits 7-0 of Line Byte Count (panel specific) bit 8 of Line Byte Count in bit 0 of AUX[03h] (panel specific) See Also AUX[00h] 0000 0000 * * * * * AUX[01h] 1000 1000 * * * * AUX[02h] 0100 1111 * * * * AUX[03h] 0000 0110 * * * see Note A at end of Table for calculation bits 7-6 = Power Save Mode 0 (application specific) bit 5 = LCD interface signals forced to 0 during Power Save (implementation specific) see Section 5.6, "Power bit 4 = no LUT bypass (application specific) Saving" on page 44 bits 3-1 = not used bit 0 = bit 8 of Line Byte Count (panel specific, see AUX[02h]) bits 7-0 = bits 7-0 of Total Display Line Count (panel specific) bits 9-8 of Total Display Line Count in bits 1-0 of AUX[05h] (panel specific) bits 7-2 = WF not required (panel specific) bits 1-0 = bits 9-8 of Total Display Line Count (panel specific, see AUX[04h]) see Note B and C at end of Table for calculation * AUX[04h] 1110 1111 * * AUX[05h] 0000 0000 * SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 9 AUX Register Data (in Binary) Notes * * bits 7-0 = bits 7-0 of Screen 1 Display Start Address (application specific) bits 15-8 of Screen 1 Display Start Address in AUX[07h] (application specific) Screen 1 Display Start Address points to D000:0000h when 0000h, Screen 1 Display Start Address is located at D000:0000h, bank 0, on the SDU1353B0C bits 7-0 = bits 15-8 of Screen 1 Display Start Address (application specific, see AUX[06h]) bits 7-0 = bits 7-0 of Screen 2 Display Start Address (application specific) bits 15-8 of Screen 2 Display Start Address in AUX[09h] (application specific) Screen 2 Display Start Address points to D000:0000h bits 7-0 = bits 15-8 of Screen 2 Display Start Address (application specific, see AUX[08h]) See Also AUX[06h] 0000 0000 AUX[07h] 1000 0000 * * * * AUX[08h] 0000 0000 * AUX[09h] 1000 0000 * * * * AUX[0Ah] 1110 1111 * * * AUX[0Bh] 1111 1100 * AUX[0Dh] 0000 0000 * see Section 4.2.1, "SDU1352B0x Evaluation Board Display Memory" on page 24 and Section 4.1, "Registers" on page 22 see Section 4.2.1, "SDU1352B0x Evaluation Board Display Memory" on page 24 and Section 4.1, "Registers" on page 22 bits 7-0 = bits 7-0 of Screen 1 Display Line Count (application specific) bits 9-8 of Screen 1 Display Line Count in bits 1-0 of AUX[0Bh] (application specific) see Section 5.4, "Split Screen 1 Display Line Count is typically the same as Total Screen" on page 34 Display Line Count (AUX[0Ah] = AUX[04h], bits 1-0 of AUX[0Bh] = bits 1-0 of AUX[05h]) bits 7-2 = not used bits 1-0 = bits 9-8 of Screen 1 Display Line Count (application specific, see AUX[0Ah]) bits 7-0 = no address pitch adjustment see Section 5.1, "Virtual Displays" on page 28 select palette address AUX[0Eh] 0000 0000 * * * bits 7-6 = bank 0 (application specific) bits 5-4 = ID bits (read only; application specific) bits 3-0 = palette address (application specific) write monochrome LUT data AUX[0Fh] 0000 0000 * bits 7-4 = N/A * bits 3-0 = palette data (application specific) AUX[0Eh] 0000 0001 increment palette address AUX[0Fh] 0000 0001 write monochrome LUT data AUX[0Eh] 0000 0010 increment palette address AUX[0Fh] 0000 0010 write monochrome LUT data AUX[0Eh] 0000 0011 increment palette address AUX[0Fh] 0000 0011 write monochrome LUT data AUX[0Eh] 0000 0100 increment palette address Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 10 Epson Research and Development Vancouver Design Center AUX Register Data (in Binary) Notes See Also AUX[0Fh] 0000 0100 write monochrome LUT data AUX[0Eh] 0000 0101 increment palette address AUX[0Fh] 0000 0101 write monochrome LUT data AUX[0Eh] 0000 0110 increment palette address AUX[0Fh] 0000 0110 write monochrome LUT data AUX[0Eh] 0000 0111 increment palette address AUX[0Fh] 0000 0111 write monochrome LUT data AUX[0Eh] 0000 1000 increment palette address AUX[0Fh] 0000 1000 write monochrome LUT data AUX[0Eh] 0000 1001 increment palette address AUX[0Fh] 0000 1001 write monochrome LUT data AUX[0Eh] 0000 1010 increment palette address AUX[0Fh] 0000 1010 write monochrome LUT data AUX[0Eh] 0000 1100 increment palette address AUX[0Fh] 0000 1100 write monochrome LUT data AUX[0Eh] 0000 1101 increment palette address AUX[0Fh] 0000 1101 write monochrome LUT data AUX[0Eh] 0000 1110 increment palette address AUX[0Fh] 0000 1110 write monochrome LUT data AUX[0Eh] 0000 1111 increment palette address AUX[0Fh] 0000 1111 write monochrome LUT data Program Mode Register bit DISP to 1, and set LCDE to enable power supply. 1001 0000b `OR' {original value for AUX[01h]} AUX[01h] 1001 1000 * * b7 = display on (application specific) b4 = LCDE = LCDENB pin = set to enable specific power supply design (for SDU1353B0C, set bit to 1 to enable power supply) (application specific) Write one pixel to the top left corner of display memory. If the SDU1352B0x evaluation board is used, video memory begins at D000:0000h; in this case write 0F0h to location D000:0000h. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 11 Note A Panel Width in Pixels Line Byte Count = ------------------------------------------------------------------------------------------- x [ bits per pixel (2 or 4 bits) ] - 1 Memory Interface Width (8 or 16 bits) 320 = -------- x 4 - 1 = 79 = 4Fh 16 B Single Panel Total Display Line Count = number of display lines - 1 = 240 - 1 = 239 = 0EFh C Dual Panel number of display lines Total Display Line Count = ------------------------------------------------------- - 1 2 Example 2: Initialize the registers for a 4 gray shade 640x480 dual panel LCD with 128k of display memory. Afterwards write one pixel to the top left corner of the display. Program SED1352 Registers 00h-0Dh: AUX Register Data (in Binary) Notes must be zero b7 = display on (normal) b6 = dual panel (panel specific) b5 = XSCL not masked (panel specific) b4 = LCDE LCDENB pin = 0 (implementation specific; the recommended procedure is to turn this bit off during register initialization and afterwards turn this bit on) b3 = 16 grays (application specific) b2 = 4 bit LCD data width (panel specific) b1 = 16 bit Memory Interface (implementation specific) b0 = RAMS ignored (implementation specific) bits 7-0 = bits 7-0 of Line Byte Count (panel specific) bit 8 of Line Byte Count in bit 0 of AUX[03h] (panel specific) See Also AUX[00h] 0000 0000 * * * * * AUX[01h] 1100 1000 * * * * AUX[02h] 0100 1111 * * * * AUX[03h] 0000 0110 * * * see Note A at end of Table for calculation bits 7-6 = Power Save Mode 0 (application specific) bit 5 = LCD interface signals forced to 0 during Power Save (implementation specific) see Section 5.6, "Power bit 4 = no LUT bypass (application specific) Saving" on page 44 bits 3-1 = not used bit 0 = bit 8 of Line Byte Count (panel specific, see AUX[02h]) bits 7-0 = bits 7-0 of Total Display Line Count (panel specific) bits 9-8 of Total Display Line Count in bits 1-0 of AUX[05h] (panel specific) bits 7-2 = WF not required (panel specific) bits 1-0 = bits 9-8 of Total Display Line Count (panel specific, see AUX[04h]) see Note B and C at end of Table for calculation * AUX[04h] 1110 1111 * * AUX[05h] 0000 0000 * Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 12 Epson Research and Development Vancouver Design Center AUX Register Data (in Binary) Notes * * bits 7-0 = bits 7-0 of Screen 1 Display Start Address (application specific) bits 15-8 of Screen 1 Display Start Address in AUX[07h] (application specific) Screen 1 Display Start Address points to C000:0000h when 0000h, Screen 1 Display Start Address is located at D000:0000h, bank 0, on the SDU1353B0C bits 7-0 = bits 15-8 of Screen 1 Display Start Address (application specific, see AUX[06h]) bits 7-0 = bits 7-0 of Screen 2 Display Start Address (application specific) bits 15-8 of Screen 2 Display Start Address in AUX[09h] (application specific) Screen 2 Display Start Address points to C000:9600h bits 7-0 = bits 15-8 of Screen 2 Display Start Address (application specific, see AUX[08h]) See Also AUX[06h] 0000 0000 AUX[07h] 0000 0000 * * * * AUX[08h] 0000 0000 * AUX[09h] 0100 1011 * * * * AUX[0Ah] 1110 1111 * * * AUX[0Bh] 1111 1100 * AUX[0Dh] 0000 0000 * see Section 4.2.1, "SDU1352B0x Evaluation Board Display Memory" on page 24 and Section 4.1, "Registers" on page 22 see Section 4.2.1, "SDU1352B0x Evaluation Board Display Memory" on page 24 and Section 4.1, "Registers" on page 22 bits 7-0 = bits 7-0 of Screen 1 Display Line Count (application specific) bits 9-8 of Screen 1 Display Line Count in bits 1-0 of AUX[0Bh] (application specific) see Section 5.4, "Split Screen 1 Display Line Count is typically the same as Total Screen" on page 34 Display Line Count (AUX[0Ah] = AUX[04h], bits 1-0 of AUX[0Bh] = bits 1-0 of AUX[05h]) bits 7-2 = not used bits 1-0 = bits 9-8 of Screen 1 Display Line Count (application specific, see AUX[0Ah]) bits 7-0 = no address pitch adjustment see Section 5.1, "Virtual Displays" on page 28 select palette address AUX[0Eh] 0000 0000 * * * * * * bits 7-6 = bank 0 (application specific) bits 5-4 = ID bits (read only; application specific) bits 3-0 = palette address (application specific) bits 7-4 = N/A bits 5-4 = bank 0 (application specific) bits 3-0 = palette data (application specific) write monochrome LUT data AUX[0Fh] 0000 0000 AUX[0Eh] 0000 0001 increment palette address AUX[0Fh] 0000 0101 write monochrome LUT data AUX[0Eh] 0000 0010 increment palette address AUX[0Fh] 0000 1010 write monochrome LUT data AUX[0Eh] 0000 0011 increment palette address AUX[0Fh] 0000 1111 write monochrome LUT data SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 13 AUX Register Data (in Binary) Notes See Also AUX[0Eh] 0000 0100 increment palette address AUX[0Fh] 0000 0000 write monochrome LUT data AUX[0Eh] 0000 0101 increment palette address AUX[0Fh] 0000 0101 write monochrome LUT data AUX[0Eh] 0000 0110 increment palette address AUX[0Fh] 0000 1010 write monochrome LUT data AUX[0Eh] 0000 0111 increment palette address AUX[0Fh] 0000 1111 write monochrome LUT data AUX[0Eh] 0000 1000 increment palette address AUX[0Fh] 0000 0000 write monochrome LUT data AUX[0Eh] 0000 1001 increment palette address AUX[0Fh] 0000 0101 write monochrome LUT data AUX[0Eh] 0000 1010 increment palette address AUX[0Fh] 0000 1010 write monochrome LUT data AUX[0Eh] 0000 1011 increment palette address AUX[0Eh] 0000 1111 increment palette address AUX[0Fh] 0000 1100 write monochrome LUT data AUX[0Fh] 0000 0000 write monochrome LUT data AUX[0Eh] 0000 1101 increment palette address AUX[0Fh] 0000 0101 write monochrome LUT data AUX[0Eh] 0000 1110 increment palette address AUX[0Fh] 0000 1010 write monochrome LUT data AUX[0Eh] 0000 1111 select palette address AUX[0Fh] 0000 1111 write monochrome LUT data Program Mode Register bit DISP to 1, and set LCDE to enable power supply. 1001 0000b `OR' {original value for AUX[01h]} AUX[01h] 1001 1000 * * b7 = display on (application specific) b4 = LCDE = LCDENB pin = set to enable specific power supply design (for SDU1353B0C, set bit to 1 to enable power supply) (application specific) Write one pixel to the top left corner of display memory. If the SDU1352B0x evaluation board is used, the first panel's memory addresses begin at C000:0000h (see Section 5.4.4.1, "Displaying a Single Image on a Dual Panel" on page 40). Consequently write 0C0h to location C000:0000h for the SDU1352B0x. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 14 Epson Research and Development Vancouver Design Center Note A Panel Width in Pixels Line Byte Count = ------------------------------------------------------------------------------------------- x [ bits per pixel (2 or 4 bits) ] - 1 Memory Interface Width (8 or 16 bits) 640 = -------- x 2 - 1 = 79 = 4Fh 16 B Single Panel Total Display Line Count = number of display lines - 1 C Dual Panel number of display lines 480 Total Display Line Count = ------------------------------------------------------- - 1 = -------- - 1 = 239 = 0EFh 2 2 SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 15 3 GRAY SHADES AND LOOK-UP TABLES This section discusses memory formats and Look-Up Table formats for the SED1352. 3.1 Pixels A pixel is physically stored in display memory as a series of bits. The more bits, the more gray shades the pixel can show. With only one bit, the pixel can only show two different combinations of gray shades (0 or 1). With two bits, the pixel can show four different combinations of gray shades (00b, 01b, 10b, or 11b). Similarly, four bits allow 16 different combinations of gray shades (0000b, 0001b, 0010b, ... 1111b). The SED1352 can be programmed to use either two bit or four bit pixels. The following sections show how these pixels are stored in display memory. 3.1.1 Two Bit Pixels To store two bit pixels, four pixels are grouped into one byte of display memory as shown below: Bit 7 Pixel 0 Bit 1 Bit 6 Pixel 0 Bit 0 Bit 5 Pixel 1 Bit 1 Bit 4 Pixel 1 Bit 0 Bit 3 Pixel 2 Bit 1 Bit 2 Pixel 2 Bit 0 Bit 1 Pixel 3 Bit 1 Bit 0 Pixel 3 Bit 0 Figure 1: Pixel Storage for 2 Bits (4 Gray Shades) In One Byte of Display Memory When these pixels are shown, Pixel 0 is seen to be left of Pixel 1, Pixel 1 is seen to be left of Pixel 2, and so on. 3.1.2 Four Bit Pixels To store four bit pixels, two pixels are grouped into one byte of display memory as shown below: Bit 7 Pixel 0 Bit 3 Bit 6 Pixel 0 Bit 2 Bit 5 Pixel 0 Bit 1 Bit 4 Pixel 0 Bit 0 Bit 3 Pixel 1 Bit 3 Bit 2 Pixel 1 Bit 2 Bit 1 Pixel 1 Bit 1 Bit 0 Pixel 1 Bit 0 Figure 2: Pixel Storage for 4 Bits (16 gray shades) in One Byte of Display Memory When these pixels are shown, Pixel 0 is seen to be left of Pixel 1. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 16 Epson Research and Development Vancouver Design Center 3.2 Look-Up Table (LUT) This section provides a concise description of the LUT registers, followed by a description of a LUT. Next is a series of examples which show how to initialize a LUT, create an inverted LUT, and how to select one of four banks in the 4 gray shade mode. 3.2.1 LUT Registers Note Register bits discussed in this section are highlighted. AUX[0E] Look-Up Table Address Register I/O address = 1110b, Read/Write Bank Bit 1 Bank Bit 0 Palette ID Bit ID Bit Address (Read Only) (Read Only) Bit 3 Palette Address Bit 2 Palette Address Bit 1 Palette Address Bit 0 The SED1352 has one internal 16 position, 4-bit wide Look-Up Table (palette). The 4-bit value programmed into each table position determines the output gray shade of display data. For example, in 16-level gray shade mode, a data value of 0001h (4 bits per pixel) will point to Look-Up Table positions one and display the 4-bit gray shade that was previously programmed into that location. bits 7-6 Bank Bits [1:0] In 4-level gray mode (2-bits/pixel), the 16 position palette is arranged into four, 4 position "banks". These two bits control which bank is currently selected. These bits have no effect in 16-level gray mode (4bits/pixel). Palette Address Bits [3:0] These 4 bits provide a pointer into the 16 position Look-Up Table currently selected for CPU R/W access. bits 3-0 Note The Look-Up Table configuration (e.g. 1/2/4 banks) does not affect the R/W access from the CPU as all 16 positions can be accessed sequentially. AUX[0F] Look-Up Table Data Register I/O address = 1111b, Read/Write. n/a bits 3-0 n/a n/a n/a Palette Data Palette Data Palette Data Palette Data Bit 3 Bit 2 Bit 1 Bit 0 Palette Data Bits [3:0] These 4-bits are the gray shade values used for display data output. They are programmed into the 4-bit Look-Up Table (palettes) positions pointed to by Palette Address bits [3:0]. For example; in a 16-level gray shade display mode, a data value of 0001b (4-bits / pixel) will point to Look-Up Table position one and display the 4-bit gray shade corresponding to the value programmed into that location. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 17 3.2.2 Look-Up Table Description The Look-Up Table (LUT, or palette) treats the value of a pixel as an index of an array of gray shades. For example, a pixel value of zero would point to the first LUT entry; a pixel value of 7 would point to the eighth LUT entry. Because LUT entries represent the actual gray shades shown on the LCD panel, pixel values indirectly select which gray shade displays. The SED1352 supports two different data formats; 4 bits-per-pixel (16 gray shades) and 2 bits-per-pixel (4 gray shades). In 4 bits-per-pixel mode the SED1352 provides a 16 position, 4 bit wide LUT. In 2 bits-per-pixel mode, the SED1352 provides 4 "banks" of 4 position, 4 bit wide LUTs. The value inside each LUT entry represents the gray shade. This value ranges between 0 and 15. The SED1352FOB Look-Up Table is linear; increasing the LUT entry number results in a lighter gray shade. For example, a LUT entry of 0Fh into a look-up entry will always result in a bright white output. An entry of 00h into a look-up entry will always result in a black output. Example 3: Initialize the Look-Up Table The following describes how to initialize the Look-Up Table for 16 gray shades. Table 3-1 shows a LUT with gray shades starting from black (index 0) and finishing in white (index 15, or 0Fh). 1. 2. 3. Write LUT index to Look-Up Table Address Register AUX[0Eh]. Write LUT entry value to Look-Up Table Data Register AUX[0Fh]. Repeat steps 1 and 2 until all 16 LUT entries have been written. Table 3-1: SED1352F0B Black-To-White Look-Up Table for 16 Gray Shades Index (hex) Look-Up Table (hex) Index (hex) Look-Up Table (hex) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F 8 9 A B C D E F Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 18 Epson Research and Development Vancouver Design Center Example 4: Initialize an Inverted Look-Up Table This example shows how to invert an image by changing only the LUT. Inverting means that pixels formally shown as light gray shades are now shown as dark gray shades, and vise versa. It does not matter whether the SED1352 is in 4 gray shade or 16 gray shade mode. 1. Read LUT entry: Write LUT index to Look-Up Table Address Register AUX[0Eh] Read "Old LUT Entry" from Look-Up Table Data Register AUX[0Fh] Calculate "New LUT Entry" according to the following formula: New LUT Entry = 15 - Old LUT Entry 2. 3. Write LUT entry back: Write LUT index to Look-Up Table Address Register AUX[0Eh] Write "New LUT Entry" to Look-Up Table Data Register AUX[0Fh] Repeat steps 1 to 3 until all 16 LUT entries have been changed. 4. If Table 3-1 was previously programmed into the SED1352, the new inverted LUT would be the following: Table 3-2: SED1352F0B Inverted Look-Up Table (White-To-Black) Index (hex) Look-Up Table (hex) Index (hex) Look-Up Table (hex) 0 1 2 3 4 5 6 7 F E D C B A 9 8 8 9 A B C D E F 7 6 5 4 3 2 1 0 SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 19 3.2.3 Four Gray Shades (Two Bits/Pixel) When the SED1352 is configured for two bit pixels, each pixel can index one of four LUT entries. In this 4 gray shade mode, the SED1352 treats the 16 entries in the LUT as four separate look-up tables or banks, each having four entries (see Figure 3). The following examples show how to program and select these banks. Example 5: 1. In 4 gray shade mode, program bank 2 LUT entries and select for use. Determine location of bank 2 in LUT. The first four entries in the 16 entry LUT represent the first bank (bank 0). The following four entries in the LUT represent the second bank (bank 1), etc. Consequently bank 2 starts at LUT index 8 as shown below: start of bank index = bank number x 4 start of bank 2 = 2 x 4 = 8 Bank 2 is shown in Figure 3, palette 2. 2. 3. Write LUT index to Look-Up Table Address Register AUX[0Eh]. For bank 2, the index will one of the following values: 08h, 09h, 0Ah, or 0Bh Write LUT entry value to Look-Up Table Data Register AUX[0Fh]. For a linear LUT, use the look-up table entries in Table 3-1, "SED1352F0B Black-To-White Look-Up Table for 16 Gray Shades," on page 17. Repeat steps 2 and 3 until all 4 LUT entries have been written. To display data using Bank 2 write 10b to AUX[0E] bits 7,6. 4. 5. Table 3-3: SED1352F0B Black-To-White Look-Up Table for 4 Gray Shades Index (hex) Look-Up Table (hex) 0 1 2 3 0 5 A F Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 20 Epson Research and Development Vancouver Design Center 4 LUTs of 4 Entries x 4 Bits LUT b3 b2 b1 b0 Index 0 0 I1I0 1 2 3 0 Palette 0 1 2 3 4 5 6 7 8 9 A B C D E F Bank Bits B1, B0 I1I0 1 2 3 0 1 2 3 0 1 2 3 Palette 1 Display Data (2 Bits/Pixel) 00 01 10 11 I1I0 I1I0 Output Value to Gray Scale Engine Palette 2 I1I0 Palette 3 Figure 3: 4-Level Gray Shade Mode Look-Up Table Architecture SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 21 3.2.4 Sixteen Gray Shades (Four Bits/Pixel) When the SED1352 has 4 bit pixels, each pixel can index into one of 16 LUT entries. The LUT bank bits are ignored in this mode. 1 LUT of 16 Entries x 4 Bits b3 b2 b1 b0 0 1 2 3 4 5 Display Data (4 Bits/Pixel) 6 7 8 9 A B C D E F I3I2I1I0 Output Value to Gray Scale Engine Figure 4: 16-Level Gray Shade Mode Look-Up Table Architecture Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 22 Epson Research and Development Vancouver Design Center 4 DISPLAY MEMORY MODELS This section introduces display memory models. A concise description of the Display Start Address Registers is provided, followed by a description of display memory. Afterwards examples are provided, illustrating how to calculate the display memory model for a given display resolution and gray level mode. Once this model is calculated, examples on programming the Display Start Address Registers are provided. 4.1 Registers Register bits discussed in this section are highlighted. AUX[01] Mode Register I/O address = 0001b, Read/Write. DISP bit 1 Panel Mask XSCL LCDE Gray Scale LCD Data Width Memory Interface RAMS Memory Interface This bit selects between the 8-bit or 16-bit memory interface. When this bit = 0, the 16-bit memory interface is selected. When this bit = 1, the 8-bit memory interface is selected. If 16-bit bus interface is selected (VD0 = 1 on RESET), the Memory Interface bit is forced to 0 internally (16-bit). This bit goes low on RESET. AUX[06] Screen 1 Display Start Address Register (LSB) I/O address = 0110b, Read/Write. Screen 1 Display Start Addr Bit 7 Screen 1 Display Start Addr Bit 6 Screen 1 Display Start Addr Bit 5 Screen 1 Display Start Addr Bit 4 Screen 1 Display Start Addr Bit 3 Screen 1 Display Start Addr Bit 2 Screen 1 Display Start Addr Bit 1 Screen 1 Display Start Addr Bit 0 AUX[07] Screen 1 Display Start Address Register (MSB) I/O address = 0111b, Read/Write. Screen 1 Display Start Addr Bit 15 Screen 1 Display Start Addr Bit 14 Screen 1 Display Start Addr Bit 13 Screen 1 Display Start Addr Bit 12 Screen 1 Display Start Addr Bit 11 Screen 1 Display Start Addr Bit 10 Screen 1 Display Start Addr Bit 9 Screen 1 Display Start Addr Bit 8 AUX[06] bits 7-0 Screen 1 Display Start Address Bits [15:0] AUX[07] bits 7-0 These 16 bits determine the Screen 1 Display Start Address. In an 8-bit memory configuration these bits set the 16-bit start address (i.e., byte access). In a 16-bit memory configuration these are the 16 most significant bits of a 17-bit start address (i.e., word access). The Screen 1 Display Start Address is the memory address corresponding to the first displayed pixel (top left corner). In a dual panel configuration, screen 1 refers to the upper half of the display. While in a single panel configuration, screen 1 refers to the first screen of the Split Screen Display feature where two different images (screen 1 and screen 2) can be displayed at the same time on one display. Note The absolute address into display memory is determined by the Memory Mapping Address which is set by VD13 - VD15. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 23 AUX[08] Screen 2 Display Start Address Register (LSB) I/O address = 1000b, Read/Write. Screen 2 Display Start Addr Bit 7 Screen 2 Display Start Addr Bit 6 Screen 2 Display Start Addr Bit 5 Screen 2 Display Start Addr Bit 4 Screen 2 Display Start Addr Bit 3 Screen 2 Display Start Addr Bit 2 Screen 2 Display Start Addr Bit 1 Screen 2 Display Start Addr Bit 0 AUX[09] Screen 2 Display Start Address Register (MSB) I/O address = 1001b, Read/Write. Screen 2 Display Start Addr Bit 15 Screen 2 Display Start Addr Bit 14 Screen 2 Display Start Addr Bit 13 Screen 2 Display Start Addr Bit 12 Screen 2 Display Start Addr Bit 11 Screen 2 Display Start Addr Bit 10 Screen 2 Display Start Addr Bit 9 Screen 2 Display Start Addr Bit 8 AUX[08] bits 7-0 Screen 2 Display Start Address Bits [15:0] AUX[09] bits 7-0 These 16 bits determine the Screen 2 Display Start Address. In an 8-bit memory configuration these bits set the 16-bit start address (i.e., byte access). In a 16-bit memory configuration these are the 16 most significant bits of a 17-bit start address (i.e., word access). In a dual panel configuration, screen 2 refers to the lower half of the display. The Screen 2 Display Start Address is the memory address corresponding to first displayed pixel in the first line of the lower half of the display. If Screen 2 is started right after Screen 1, the Screen 2 Display Start Address is calculated with the following formula. Screen2DisplayStartAddress ( hex ) = ( ImageHorizontalResolution ) x ( ImageVerticalResolution ) x ( BytesPerPixel ) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Screen1DisplayStartAddress MemoryInterfaceWidth 2 x ---------------------------------------------------------------- 8 In a single panel configuration, screen 2 refers to the second screen of the Split Screen Display Feature where two different images (screen 1 and screen 2) can be displayed at the same time on one display. The Screen 2 Display Start Address is the memory address corresponding to the first pixel of the second image stored in display memory. To display screen 2 refer to AUX[0A] Screen 1 Display Line Count Register (LSB) below. . Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 24 Epson Research and Development Vancouver Design Center 4.2 Description When displaying an image, the SED1352 must read pixel data from display memory. This memory is organized to match the display resolution of the given LCD panel. To organize display memory, the following registers must be programmed: 1. 2. 3. Screen 1 Display Start Address Registers. Screen 2 Display Start Address Registers. Address Pitch Adjustment Register. For the first example, the Address Pitch Adjustment Register is programmed to zero. This means that no virtual display is available; for information on virtual displays see Section 5.1, "Virtual Displays" on page 28. 4.2.1 SDU1352B0x Evaluation Board Display Memory There are several issues to consider when programming the Screen Display Start Address Registers for the SDU1352B0x evaluation board: * When the SDU1352B0x is set for 64k of display memory, display memory exists from address D000:0000h to address D000:FFFFh. When the SDU1352B0x is set for 128k of display memory, display memory exists from address C000:0000h to address D000:FFFFh. For the SDU1352B0x, the Screen Display Start Address Registers are always in reference to the display memory address C000:0000h. Writing 0 to a Display Start Address Register will always refer to C000:0000h, even if display memory only exists from D000:0000h to D000:FFFFh. Consequently if only 64k of display memory is present, 64k must be added to the display address in order to point to D000:0000h. This is a limitation of the evaluation board only. Although the SED1352 can set the Memory Interface to 8 or 16 bits, the SDU1352B0x evaluation board should be set up for 16 bits. As a result, the Display Start Address Registers are word pointers, not byte pointers. To illustrate how to use a word pointer, refer to Example 6. In general, any system which uses more than 64k of display memory must always have the Memory Interface set to 16 bits. * * Example 6: For the SDU1352B0x, calculate the required start address register value which refers to location D000:0000h. Since a value of 0 refers to location C000:0000h, the start address register must be programmed with an offset address of 1000:0000h = 10000h bytes, or 8000h words. START ADDRESS[LSB] = 00h START ADDRESS[MSB] = 80h SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 25 4.2.2 Display Start Address Registers This section illustrates how to properly calculate the values for the Screen Start Address Registers for a given LCD panel resolution. However, this section is limited to single panel displays; refer to Section 5.4.4, "Dual Panel LCD" on page 38 to program the Screen Start Address Registers for a dual panel display. In the following example, the Display Start Address Registers are programmed for a 16 gray shade 320 x 240 single monochrome display. The technique shown, however, can also be used to calculate the memory map of other resolutions. In addition, reference is made to the SDU1352B0x evaluation board; other hardware implementations of the SED1352 may assign different display and port addresses from those of the SDU1352B0x. Refer to the SDU1352B0x Evaluation Board User's Manual for more information on these hardware issues. Example 7: Program the Display Start Address Registers for a 16 gray shade 320 x 240 single monochrome LCD panel; the display is attached to the SDU1352B0x evaluation board with 64k of display memory. 1. Calculate the number of bytes per scan line. 16 gray shades => 4 bits per pixel 4 bits per pixel => 2 pixels per byte pixels per scan line 320 number of bytes per scan line = --------------------------------------------- = -------- = 160 bytes per scan line = 00A0h bytes per scan line pixels per byte 2 2. Calculate the total number of bytes required for display memory. ( bytes per scan line ) x ( number of scan lines ) = 160 x 240 = 38400 bytes = 9600h bytes 3. Create the memory map. Each scan line is 00A0h bytes long, there are 240 scan lines, and the last memory address is 9600h - 1. Offset (hex) 0000 00A0 Scan Line 0 Scan Line 1 Offset (hex) 009F 013F 94C0 9560 Scan Line 238 Scan Line 239 955F 95FF Figure 5: Memory Map for 320 x 240 LCD Panel with 16 Gray Shades 4. Program the Screen 1 Display Start Address Registers. Assume that the image starts at the beginning of display memory, which for 64k is D000:0000h. As shown in Example 6, the Screen 1 Display Start Address Registers must be programmed to 8000h words. AUX[06h] = 00h AUX[07h] = 80h Program the Screen 2 Display Start Address Registers. Under normal programming conditions, the Screen 2 Display Start Address should be set to the same value as the Screen 1 Display Start Address. In the event that a split screen is required, refer to Section 5.4, "Split Screen" on page 34. AUX[08h] = 00h AUX[09h] = 80h 5. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 26 Epson Research and Development Vancouver Design Center Example 8: Program the Display Start Address Registers for a dual panel LCD. Refer to Section 5.4.4.1, "Displaying a Single Image on a Dual Panel" on page 40. Example 9: 1. Determine if the SED1352 implementation can support a 640x480 LCD with 4 gray shades. Calculate the number of bytes per scan line: pixels per scan line 640 --------------------------------------------- = -------- = 160 bytes per scan line pixels per byte 4 2. Calculate the total number of bytes required for display memory: ( 160 bytes per scan line ) ( 480 scan lines ) = 76800 bytes 3. Compare the required number of bytes with the amount of memory available to the SED1352. * * If the SED1352 has 128k available, there is 131,072 bytes available, which is greater than the 76,800 bytes required for 640 x 480 with 4 gray shades. If the SED1352 has 64k available, there is 65,536 bytes available, which is less than the 76,800 bytes required for 640 x 480 with 4 gray shades. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 27 4.3 Common Display Memory Requirements for LCD Panel Sizes The following is a list of memory requirements and memory maps for common LCD resolutions. Note that the memory required for 640x480 with 16 gray shades exceeds 128k and is therefore not supported on the SED1352. Table 4-1: Memory Size Requirements Display Resolution 320x240 640x200 640x480 Pixel Storage Bits/Pixel Gray Shades 2 4 4 16 2 4 4 16 2 4 4 16 Memory Requirements Bytes Hex 19,200 0000 4B00 38,400 0000 9600 32,000 0000 7D00 64,000 0000 FA00 76,800 0001 2C00 N/A N/A Offset (hex) 0000 0050 Scan Line 0 Scan Line 1 Offset (hex) 004F 009F 4A60 4AB0 Scan Line 238 4AAF Scan Line 239 4AFF Figure 6: Memory Map Example for 320 x 240 LCD Panel with 4 Gray Shades Offset (hex) 0000 0140 Scan Line 0 Scan Line 1 Offset (hex) 013F 027F F780 F8C0 Scan Line 198 Scan Line 199 F8BF F9FF Figure 7: Memory Map Example for 640 x 200 LCD Panel with 16 Gray Shades Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 28 Epson Research and Development Vancouver Design Center 5 ADVANCED TECHNIQUES This section presents information on the following: * * * * * * virtual displays bitmaps and text displays reading and writing to the SED1352 registers split screen displays panning and scrolling. power saving. 5.1 Virtual Displays This section presents a detailed description of the Address Pitch Adjustment Register, followed by a description of a virtual display. Afterwards an example is given, showing how to create a virtual display. 5.1.1 Registers Note Register bits discussed in this section are highlighted. AUX[0D] Address Pitch Adjustment Register I/O address = 1101b, Read/Write. Addr Pitch Adjustment Bit 7 bits 7-0 Addr Pitch Adjustment Bit 6 Addr Pitch Adjustment Bit 5 Addr Pitch Adjustment Bit 4 Addr Pitch Adjustment Bit 3 Addr Pitch Adjustment Bit 2 Addr Pitch Adjustment Bit 1 Addr Pitch Adjustment Bit 0 Addr Pitch Adjustment Bits [7:0] These bits set the numerical difference between the last address of a display line, and the first address in the following line. If the Address Pitch Adjustment is not equal to zero, then a virtual screen is formed. The size of the virtual screen is only limited by the available display memory. The actual display output is a window that is part of the whole image stored in the display memory. For example, with 128K of display memory, a 640x400 16-gray image can be stored. If the output display size is 320x240, then the whole image can be seen by changing display starting addresses through AUX[06] and [07], and AUX[08] and [09]. Note that a virtual screen can be produced on either a single or dual panel. In 8-bit memory interface, if the Address Pitch Adjustment is not equal to zero, then a virtual screen with a line length of (Line Byte Count +AUX[0D]) bytes is created, with the display reflecting the contents of a window (Line Byte Count+1) bytes wide. The position of the window on the virtual screen is determined by AUX[06] and [07], and AUX[08] and [09]. In 16-bit memory interface, if the Address Pitch Adjustment is not equal to zero, then a virtual screen with a line length of 2*(Line Byte Count +AUX[0D]) bytes is created, with the display reflecting the contents of a window 2*(Line Byte Count+1) bytes wide. The position of the window on the virtual screen is determined by AUX[06] and [07], and AUX[08] and [09]. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 29 5.1.2 Description The SED1352 can be programmed to use memory offsets in such a way that the physical display behaves as a viewport into a much larger "virtual" memory space. This viewport can be panned and/or scrolled to display this larger memory space. Referring to the figure below, a virtual image of 640x480 can be viewed by navigating the 320x240 viewport around the image by panning and scrolling . 320x240 Viewport 640x480 "Virtual" Display Figure 8: 640 x 480 Virtual Display To create a virtual display, the Address Pitch Adjustment Register must be programmed to indicate the horizontal size of the larger, "virtual" image stored in display memory. The Address Pitch Adjustment Register tells the SED1352 how many bytes or words of display memory are part of the nonvisible region of display memory (see Example 10). Example 10: Program the Address Pitch Adjustment Register to support a 16 gray shade 640x480 virtual display on a 320x240 LCD panel; the Memory Interface is 16 bits. 1. 2. 3. Initialize the SED1352 registers for a 320x240 panel. Determine whether the Address Pitch Adjustment Register refers to bytes or words. Since the Memory Interface is set to 16 bits, the Address Pitch Adjustment Register refers to words. Determine the number of pixels per unit referred to by the Address Pitch Adjustment Register. The Address Pitch Adjustment Register refers to units of words, so find the number of pixels per word. 16 gray shades => 4 bits per pixel 4 bits per pixel => 2 pixels per byte pixels per word = ( pixels per byte ) x 2 = 2 x 2 = 4 pixels per word 4. Calculate the number of pixels on a horizontal scan line not visible. ( virtual display width in pixels ) - ( panel width in pixels ) = 640 - 320 = 320 hidden pixels Consequently on a screen update the SED1352 will show the first 320 of 640 pixels, and then ignore the remaining 320 pixels in order to reach the next scan line. 5. Program the Address Pitch Adjustment Register: number of hidden horizontal pixels 320 ----------------------------------------------------------------------------------- = -------- = 80 words = 50h words pixels per word 4 Therefore AUX[0Dh] = 50h 6. To view the rest of the image refer to Section 5.5, "Panning and Scrolling" on page 42, keeping in mind that the horizontal width is 640 pixels, not 320. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 30 Epson Research and Development Vancouver Design Center 5.2 Bitmaps and Text Displays For the scope of this guide, a bitmap is a data structure which represents the image shown on the LCD. The bitmap includes the dimensions of the image, and the gray shade palette used to program the look-up table. Text is shown by creating a font, which in this example is a series of bitmaps, one bitmap per alphanumeric character. Example 11: Display the word "TEXT" on a 16 gray shade 320x240 LCD panel; the Memory Interface is 16 bits. 1. Define the font for the letters `T', `E', and `X'. Each character is 8x8 pixels, with at least one horizontal and vertical side left blank for spacing. Figure 9: Font for the Message "TEXT" 2. 3. 4. Program the Look-up Table. See Example 3, "Initialize the Look-Up Table," on page 17. Calculate the display memory map. See Figure 5, "Memory Map for 320 x 240 LCD Panel with 16 Gray Shades," on page 25. Write font to display memory. In a general purpose program the entire bitmapped font would be placed in an array. As characters are to be displayed, the program would choose the appropriate bitmap, select the proper position on the screen, and write to display memory. For this example assume that the program has already selected the proper bitmaps and the correct positions in display memory (there is a detailed programming example later in this guide; see Section 6.3, "Advanced Functions" on page 52). Each highlighted pixel in the text bitmap will be shown at maximum intensity, which is pixel value 15. The text, for simplicity, will be shown in the upper left corner of the screen. When the program has completed writing the pixels for the word "TEXT," the display memory will have the data shown in Figure 10. In this figure the bytes are grouped within vertical lines. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 31 Offset (hex) 0000 00A0 0140 01E0 0280 0320 03C0 0460 F FFFFF0 0FFFFFFF0FF0 00FF0 FFFFFF00 F0FF0F000FF000F0FF000FF0F0FF0F00 0 0 FF0 00 00 FF0F00 00 FF0FF00 00 FF00 00 0 0 FF0 00 00 FFFF00 00 0FFF0 00 00 FF00 00 0 0 FF0 00 00 FF0F00 00 0FFF0 00 00 FF00 00 0 0FF00000FF000F00FF0FF0000FF0000 0 FFFF00 0FFFFFFF0FF0 00FF0 0FFFF0 00 0 0000000000000000000000000000000 Figure 10: Display Memory Contents for Message "TEXT" Offset (hex) 000F 00AF 014F 01EF 028F 032F 03CF 046F Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 32 Epson Research and Development Vancouver Design Center 5.3 Registers The SED1352 has an internal set of sixteen 8-bit read/write registers which configure it for various modes of operation. The registers can be accessed in two ways: Indexed Addressing and Direct Addressing. Note Refer to the SED1352 Hardware Functional Specification and SDU1352B0x Evaluation Board User's Manual for more information on the SED1352 registers. 5.3.1 Indexed Addressing This method requires only two sequential I/O address locations starting from the base I/O address. The base I/O address is determined by the power-on state of the SRAM data lines VD[4-12]. See Table 5-6 in the SED1352 Hardware Functional Specification, X16-SP-001-xx. The two sequential I/O addresses are defined as Index Address and Data. To access registers using this method, an Index Address must be written to the first I/O address location allowing data to be written/read to/from the second I/O address. Example 12: Write 12h to register 08h on the SDU1352B0x evaluation board; the base port address is 310h, and indexed port mapping is used. 1. Write 08h to the index register. The index register is at base port address + 0 = 310h. MOV DX,310h MOV AL,08h OUT DX,AL 2. Write 12h to the data register. The data register is at base port address + 1 = 311h. MOV DX,311h MOV AL,12h OUT DX,AL 5.3.2 Direct Addressing This method of addressing requires 16 sequential I/O addresses starting from the base I/O address. The base I/O address is determined by the power-on state of the SRAM data lines VD[7-12]. See Table 5-6 in the SED1352 Hardware Functional Specification, X16-SP-001-xx. To access the internal 16 registers of the SED1352, simply perform I/O read/write functions to the absolute address as defined in the previous paragraph. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 33 Example 13: Write 12h to register 08h on the SDU1352B0x evaluation board; the base port address is 310h, and direct port mapping is used. 1. Calculate the port address for register 08h. port address = 310h + 8h = 318h 2. Write the value 12h to port address 318h. MOV DX,318h MOV AL,12h OUT DX,AL Note The SDU1352B0x is normally configured for register indexing, not direct mapping. Refer to the SDU1352B0x Evaluation Board User's Manual for more information configuring the SDU1352B0x board for register indexing or register direct mapping. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 34 Epson Research and Development Vancouver Design Center 5.4 Split Screen This section describes how to create a split screen for both single and dual LCD panels. For single panel displays, the Screen 1 Display Line Count Registers are used. For dual panel displays, the Screen 2 Display Start Address Registers are used. 5.4.1 Registers AUX[0A] Screen 1 Display Line Count Register (LSB) I/O address = 1010b, Read/Write. Screen 1 Display Line Count Bit 7 Screen 1 Display Line Count Bit 6 Screen 1 Display Line Count Bit 5 Screen 1 Display Line Count Bit 4 Screen 1 Display Line Count Bit 3 Screen 1 Display Line Count Bit 2 Screen 1 Display Line Count Bit 1 Screen 1 Display Line Count Bit 0 This register is used to enable the split screen display feature (single panel only) where two different images can be displayed at the same time on one display. This register has no effect when using a dual panel configuration. bits 7-0 Screen 1 Display Line Count Bits [7:0] These bits are the seven LSB of a 9-bit value used to determine the number of lines displayed for screen 1. The remaining lines will automatically display from the screen 2 display start address. The 9-bit value programmed is the number of display lines -1. For example, if AUX[0A] = 20h for a 320x240 display system. The display will show 20h+1 = 33 lines on the upper part of the screen according to display starting address AUX[06] and AUX[07] and 240 - 33 = 207 lines on the lower part of the screen according to display starting address AUX[08] and AUX[09]. Two different images can be displayed when using a dual panel configuration by changing the screen 2 display start address. However, by using this method screen 2 is limited to the lower half of the display. AUX[0B] Screen 1 Display Line Count Register (MSB) I/O address = 1011b, Read/Write. Screen 1 Display Line Count Bit 9 Screen 1 Display Line Count Bit 8 n/a n/a n/a n/a n/a n/a bits 1-0 Screen 1 Display Line Count Bits [9:8] These are the two MSB of the Screen 1 Display Line Count Register. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 35 5.4.2 Description A split screen is generally considered as the presentation of two different images on the screen. Image 1 is shown on the top half and image 2 is shown on the bottom half of the screen. Due to the design the SED1352, the system is always in split screen mode. If only one image is to be shown, either image 2 is hidden or image 2 appears as part of image 1; this depends on whether a single or dual panel LCD is in use. 5.4.3 Single Panel LCD The following is the procedure to show a split screen image on a 16 gray shade 320 x 240 single panel LCD. For this example the SDU1352B0x is used; the Memory Interface is set to 16 bits, and 128k of display memory is available. In addition, the two images shown on the split screen are each 320x240; only a portion of each image is shown. 1. Determine whether the Display Start Address Registers refer to bytes or words. Since the Memory Interface is set to 16 bits, the Display Start Address Registers refer to words. Note that when addresses refer to words, the image must be aligned in memory such that the beginning is found on a word boundary (the least significant bit of the memory address must be 0). Calculate the number of bytes per scan line. 16 gray shades => 4 bits per pixel 4 bits per pixel => 2 pixels per byte 320 pixels per scan line number of bytes per scan line = --------------------------------------------- = -------- = 160 bytes per scan line = 00A0h bytes per scan line pixels per byte 2 2. 3. Determine the display memory location for image 1. For simplicity, assign the beginning of display memory as the starting address of image 1 (see Figure 11). For the SDU1352B0x, this address is C000:0000h. Display Memory Screen 1 Display Start Address C000:0000h Image 1 Screen 2 Display Start Address C000:9600h (for this example) Image 2 Figure 11: Memory Map for Split Screen 4. Program the Screen 1 Display Start Address Register to point to the beginning of image 1. Since image 1 is at the beginning of display memory for a 128k system, program the Screen 1 Display Start Address Register to 0000h. AUX[06h] = 00h AUX[07h] = 00h Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 36 Epson Research and Development Vancouver Design Center 5. Calculate the total number of bytes required for image 1. ( bytes per scan line ) x ( number of scan lines for image 1 ) = 160 x 240 = 38400 bytes = 9600h bytes 6. Determine the display memory location for image 2. Place image 2 immediately after image 1 (see Figure 11). Assign the starting address for image 2 as follows: image 2 address = ( base display memory address ) + ( size of image 1 ) = C000:0000h + 0000:9600h = C000:9600h 7. Program the Screen 2 Display Start Address Register to point to the beginning of image 2. Image 2 is placed right after image 1, as shown below: size of image 1 in bytes Screen 2 Display Start Address = Screen 1 Display Start Address + -------------------------------------------------------2 bytes per word 9600h = 0000h + -------------- = 4B00h 2 AUX[08h] = 00h AUX[09h] = 4Bh 8. Program the Screen 1 Display Line Count Register. The Display Line Count Register indicates how many lines of the first screen should be shown minus 1. By changing the line count, image 2 appears to move up or down the display. * If the line count is set to the maximum number of visible scan lines - 1, only image 1 is shown. visible scan lines - 1 = 240 - 1 = 239 = 00EFh AUX[0Ah] = LSB of (visible scan lines - 1) = 0EFh AUX[0Bh] = MSB of (visible scan lines - 1) = 00h * If the line count is set to 0, then the first scan line of image 1 is shown followed by the first part of image 2. AUX[0Ah] = 00h AUX[0Bh] = 00h It is not possible to show only image 2 by changing the line count. If only image 2 needs to be shown, reprogram the Screen 1 Display Start Address Registers to point to the beginning of image 2, and set the line count to the maximum number of visible scan lines - 1. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 37 * If the line count is set to 99, then the first 100 scan lines of image 1 are shown, following by the first part of image 2 (see Figure 12). AUX[0Ah] = 63h (99 decimal) AUX[0Bh] = 00h Scan Line 0 ... Scan Line 99 Scan Line 100 ... Scan Line 239 Screen 1 Display Line Count Register = 99 lines Figure 12: 320 x 240 Single Panel for Split Screen Image 2 Image 1 9. Write both image 1 and image 2 to their respective locations in display memory. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 38 Epson Research and Development Vancouver Design Center 5.4.4 Dual Panel LCD The following is the procedure to show a split screen image on a 4 gray shade 640x480 dual panel LCD. For this example the SDU1352B0x is used; the Memory Interface is set to 16 bits, and 128k of display memory is available. In addition, the two images shown on the split screen are each 640x240. 1. Determine whether the Display Start Address Registers refer to bytes or words. Since the Memory Interface is set to 16 bits, the Display Start Address Registers refer to words. Note that when addresses refer to words, the image must be aligned in memory such that the beginning is found on a word boundary (the least significant bit of the memory address must be 0). Calculate the number of bytes per scan line. 4 gray shades => 2 bits per pixel 2 bits per pixel => 4 pixels per byte pixels per scan line 640 number of bytes per scan line = --------------------------------------------- = -------- = 160 bytes per scan line = 00A0h bytes per scan line pixels per byte 4 2. 3. Determine the display memory location for image 1. For simplicity, assign the beginning of display memory as the starting address of image 1 (see Figure 11). For the SDU1352B0x, this address is C000:0000h. Program the Screen 1 Display Start Address Register to point to the beginning of image 1. Since image 1 is at the beginning of display memory for a 128k system, program the Screen 1 Display Start Address Register to 0000h. AUX[06h] = 00h AUX[07h] = 00h Calculate the total number of bytes required for image 1. ( bytes per scan line ) x ( number of scan lines for image 1 ) = 160 x 240 = 38400 bytes = 9600h bytes 4. 5. 6. Determine the display memory location for image 2. Place image 2 immediately after image 1 (see Figure 11). Assign the starting address for image 2 as follows: image 2 address = ( base display memory address ) + ( size of image 1 ) = C000:0000h + 0000:9600h = C000:9600h 7. Program the Screen 2 Display Start Address Register to point to the beginning of image 2. Image 2 is placed right after image 1, as shown below: size of image 1 in bytes Screen 2 Display Start Address = Screen 1 Display Start Address + -------------------------------------------------------2 bytes per word 9600h = 0000h + -------------- = 4B00h 2 AUX[08h] = 00h AUX[09h] = 4Bh 8. Write both image 1 and image 2 to their respective locations in display memory. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 39 Notes When using a dual panel, the Screen 1 Display Line Count Register is ignored by the SED1352. Once the two Display Start Address Registers are programmed, the top panel will show the beginning of image 1, and the bottom panel will show the beginning of image 2 (see Figure 13). Scan Line 0 ... Scan Line 239 Scan Line 240 ... Scan Line 479 Screen 1 Display Line Count is ignored; Image 1 always has half the total number of scan lines (240 in this example). Figure 13: 640 x 480 Dual Panel for Split Screen Each image can be scrolled or panned by appropriate programming of the respective Display Start Address Registers. The following are some examples: * To scroll image 1 up, the Screen 1 Start Address Register must point to the following scan line. number of bytes per scan line Screen 1 Display Start Address = Screen 1 Display Start Address + ---------------------------------------------------------------------2 bytes per word Image 1 Image 2 AUX[06h] = LSB of Screen 1 Display Start Address AUX[07h] = MSB of Screen 1 Display Start Address * To scroll image 2 down, the Screen 2 Start Address Register must point to the previous scan line. number of bytes per scan line Screen 2 Display Start Address = Screen 2 Display Start Address - ---------------------------------------------------------------------2 bytes per word AUX[08h] = LSB of Screen 2 Display Start Address AUX[09h] = MSB of Screen 2 Display Start Address * To pan image 1 to the right by a group of pixels, the Screen 1 Start Address Register must be increased by 1. Screen 1 Display Start Address = Screen 1 Display Start Address + 1 AUX[06h] = LSB of Screen 1 Display Start Address AUX[07h] = MSB of Screen 1 Display Start Address See Section 5.5.2, "Panning Right and Left" on page 42 for more information. * To pan image 2 to the left by a group of pixels, the Screen 2 Start Address Register must be decreased by 1. Screen 2 Display Start Address = Screen 2 Display Start Address - 1 AUX[08h] = LSB of Screen 2 Display Start Address AUX[09h] = MSB of Screen 2 Display Start Address See Section 5.5.2, "Panning Right and Left" on page 42 for more information. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 40 Epson Research and Development Vancouver Design Center 5.4.4.1 Displaying a Single Image on a Dual Panel The following is the procedure to show a single image on a dual panel LCD. In this procedure the single image is broken into two smaller images; image 1 is placed on the top panel and image 2 is placed on the bottom panel. For this example the SDU1352B0x is used with a 4 gray shade 640x480 dual panel LCD; the Memory Interface is set to 16 bits, and 128k of display memory is available. 1. Determine whether the Display Start Address Registers refer to bytes or words. Since the Memory Interface is set to 16 bits, the Display Start Address Registers refer to words. Note that when addresses refer to words, the image must be aligned in memory such that the beginning is found on a word boundary (the least significant bit of the memory address must be 0). Calculate the number of bytes per scan line. 4 gray shades => 2 bits per pixel 2 bits per pixel => 4 pixels per byte pixels per scan line 640 number of bytes per scan line = --------------------------------------------- = -------- = 160 bytes per scan line = 00A0h bytes per scan line pixels per byte 4 2. 3. Determine the display memory location for image 1. For simplicity, assign the beginning of display memory as the starting address of image 1 (see Figure 14). For the SDU1352B0x, this address is C000:0000h. Display Memory Screen 1 Display Start Address First half of Image Screen 2 Display Start Address Second half of Image Figure 14: Memory Map for a Dual Panel showing a Single Image 4. Program the Screen 1 Display Start Address Register to point to the beginning of image 1. Since image 1 is at the beginning of display memory for a 128k system, program the Screen 1 Display Start Address Register to 0000h. AUX[06h] = 00h AUX[07h] = 00h Determine the size of image 1. 480 number of scan lines in display vertical size of image 1 = vertical size of panel 1 = -------------------------------------------------------------------------- = -------- = 240 scan lines 2 2 display width in pixels 640 size = ----------------------------------------------------- x ( number of scan lines in image 1 ) = -------- x 240 = 38400 bytes = 9600h bytes 4 pixels per byte 5. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 41 6. Determine the display memory location for image 2. Place image 2 immediately after image 1 (see Figure 14). Assign the starting address for image 2 as follows: image 2 address = ( base display memory address ) + ( size of image 1 ) = C000:0000h + 0000:9600h = C000:9600h 7. Program the Screen 2 Display Start Address Register to point to the beginning of image 2. Image 2 is placed right after image 1, as shown below: size of image 1 in bytes Screen 2 Display Start Address Register = Screen 1 Display Start Address Register + -------------------------------------------------------2 bytes per word 9600h = 0000h + -------------- = 4B00h 2 AUX[08h] = 00h AUX[09h] = 4Bh 8. Write both image 1 and image 2 to their respective locations in display memory. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 42 Epson Research and Development Vancouver Design Center 5.5 Panning and Scrolling Panning and scrolling are typically used to show an image which is too large to be shown completely on an LCD panel. Although the image is stored entirely in display memory, only a small portion is actually visible on the LCD panel. This visible portion is called the viewport; the user moves this viewport over different portions of the image by panning and scrolling. Panning moves the viewport right or left. Scrolling moves the viewport up or down. 5.5.1 Initialization To pan and scroll over a large image, the SED1352 registers must first be initialized and the image written to display memory. To do so, initialize the registers as described in Section 2, "INITIALIZING THE SED1352" on page 8, but with the following exception: the Address Pitch Adjustment Register in the SED1352 must be set to create a virtual display; see Section 5.1, "Virtual Displays" on page 28 for more information. 5.5.2 Panning Right and Left To pan to the right, increase the value in the Screen 1 Display Start Address Register. To pan to the left, decrease the value in the Screen 1 Display Start Address Register. Note that the SED1352 can pan right or left by either 2, 4, or 8 pixels. This is because the Screen 1 Display Start Address Register refers to either bytes or words (see Section 4.2.1, "SDU1352B0x Evaluation Board Display Memory" on page 24), and a byte can represent either 2 or 4 pixels, and so a word can represent 4 or 8 pixels; see Table 5-1 below: Table 5-1: Smallest Number of Pixels for Panning Memory Interface 8 bits 16 bits Gray Levels 4 16 4 16 Pixels per Byte 4 2 4 2 Smallest Number of Pixels for Panning 4 2 8 4 5.5.3 Scrolling Up and Down To scroll up, increase the value in the Screen 1 Display Start Address Register by the number of bytes in one virtual scan line. To scroll down, decrease the value in the Screen 1 Display Start Address Register by the number of bytes in one virtual scan line. A virtual scan line is in reference to a virtual display, in which an image larger than the physical size of the LCD is stored. The number of bytes in a virtual scan line is the number of bytes required to store one horizontal line of pixels in the virtual image. Example 14: Scroll down one line for a 16 gray shade 640x200 virtual image using a 320x240 single panel LCD. The Memory Interface is 16 bits, and 64k of display memory is available. Also describe how to scroll in a dual panel LCD. 1. Calculate the number of bytes in a virtual scan line. 640 pixels per scan line number of horizontal pixels in virtual image --------------------------------------------------------------------------------------------------------- = ------------------------------------------------------- = 320 bytes per scan line 2 pixels per byte number of pixels per word SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 43 2. Add the number of words in a virtual scan line to the Screen 1 Display Start Address Register. In this example the Screen 1 Display Start Address points to the beginning of the image. number of bytes in a virtual scan line Screen 1 Display Start Address = Screen 1 Display Start Address + ---------------------------------------------------------------------------------------2 bytes per word 320 = 8000h + -------2 = 80A0h 3. Program the Screen 1 Display Start Address. AUX[06h] = A0h AUX[07h] = 80h FOR DUAL PANELS ONLY Add the number of words in a virtual scan line to the Screen 2 Display Start Address Register. In this example the Screen 2 Display Start Address has previously been initialized as described in Section 5.4.4.1, "Displaying a Single Image on a Dual Panel" on page 40. number of bytes in a virtual scan line Screen 2 Display Start Address = Screen 2 Display Start Address + ---------------------------------------------------------------------------------------2 bytes per word 4. 5. FOR DUAL PANELS ONLY Program the Screen 2 Display Start Address. AUX[08h] = least significant byte of "Screen 2 Display Start Address" AUX[09h] = most significant byte of "Screen 2 Display Start Address" Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 44 Epson Research and Development Vancouver Design Center 5.6 Power Saving The following section introduces the power saving capabilities of the SED1352. A detailed description of the Power Save Register is provided, followed by a description of the power save modes. 5.6.1 Registers Note Register bits discussed in this section are highlighted. AUX[03] Line Byte Count (MSB [bit 8] for 16-level gray scale mode only) / Power Save Register I/O address = 0011b, Read/Write PS Bit 1 bits 7-6 PS Bit 0 LCD Signal LUT State Bypass n/a n/a n/a Line Byte Count Bit 8 PS Bits [1:0] Selects the Power Save Modes as shown in the following table. The PS bits [1:0] go to 0 on RESET. Table 5-2: Power Save Mode Selection PS1 0 0 1 1 PS0 0 1 0 1 Mode Activated Normal Operation Power Save Mode 1 Power Save Mode 2 Reserved Refer to Section 5.6.2, "Power Save Modes" on page 44 for a complete Power Save Mode description. 5.6.2 Power Save Modes Two software-controlled Power Save Modes have been incorporated into the SED1352 to accommodate the important need for power reduction in hand-held devices market. These modes can be enabled by setting the 2 Power Save bits (AUX[03h] bits 7-6). The various settings are: Table 5-3: Power Save Mode Selection Bit 7 Bit 6 0 0 0 1 1 0 1 1 Mode Activated Normal Operation Power Save Mode 1 Power Save Mode 2 Reserved 5.6.2.1 Power Save Mode 1 Power Save Mode 1 would typically be used when power savings are required and memory accesses may occur. The disadvantage is that since the oscillator is running, this mode consumes more power that Power Save Mode 2. 5.6.2.2 Power Save Mode 2 Power Save Mode 2 is typically used when memory accesses would not occur. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 45 5.6.2.3 Power Save Mode Function Summary Table 5-4: Power Save Mode Function Summary Power Save Mode (PSM) Function Normal (Active) Yes Yes Yes Yes No PSM1 State 1 No Yes Yes No No State 2 No Yes No No No PSM2 Display Active? I/O Access Possible? Memory Access Possible? Sequence Controller Running? Internal Oscillator Disabled? No Yes No No Yes Note 1. When programming the PS bits do a read/modify/write operation so as not to destroy any other data in the register. 2. Refer to the programming example in Advanced Functions on page 52. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 46 Epson Research and Development Vancouver Design Center 6 PROGRAMMING THE SED1352 The purpose of this section is to show how to program the SED1352 exercising the specific capabilities of this chip. A series of functions written in `C' will be presented, each illustrating a basic feature of the SED1352. These functions are written for the SDU1352B0x evaluation board, and are combined under a menu-driven program called DEMO.EXE. Note The sample code will not run on a display larger than 320x240, and will use 16 gray shades in most of the examples. This program accepts the following command line options: DEMO type x=n y=n p=n where: type = SINGLE | DUAL x = horizontal panel size in pixels from 1 to 320 (decimal) y = vertical panel size in pixels from 1 to 240 (decimal) p = 300 | 310...360 | 370 (port address in hex) (I/O indexed addressing selected by default) For example, if there is a 320x240 single panel LCD with a port address of 310h, type DEMO SINGLE x=320 y=240 p=310 When DEMO is started, output will be sent to the standard output device. This output will present a menu of numbered options: SDU1352B0x DEMO PROGRAM Press 1 to read registers Press 2 to show gray shade bar Press 3 to show split screen Press 4 to show panning and scrolling Press 5 to start power saving Press ESC to quit Figure 15: Display for DEMO.EXE SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 47 6.1 Main Loop Code //------------------------------------------------------------------------// // FUNCTION: main() // // DESCRIPTION: Start of demo program. // // INPUTS: Command line arguments. // RETURN VALUE: None. // //------------------------------------------------------------------------void main(char argc, char **argv) { int ch; CheckArguments(argc, argv); printf("Initializing\n"); Initialize(); ClearLCDScreen(); ShowMenu(); while ((ch = getch()) != ESC) { switch (ch) { case '1': ShowRegisters(); break; case '2': GrayShadeBars(); break; case '3': SplitScreen(); break; case '4': PanScroll(); break; case '5': PowerSaving(); break; case ESC: exit(0); } } } Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 48 Epson Research and Development Vancouver Design Center 6.2 Initialization Code //------------------------------------------------------------------------// // FUNCTION: Initialize() // // DESCRIPTION: Intialize SED1352 registers. // // INPUTS: This function looks at the followingl global variables to // determine the appropriate register settings: // PanelX, PanelY, PanelType // // OUTPUTS: The following global variables are changed: // PanelGrayLevel, BytesPerScanLine // //------------------------------------------------------------------------void Initialize(void) { static unsigned int val; static unsigned int x; PanelGrayLevel = 16; //-------------------------------------// // Mode Register: // Display = ON // Panel = SINGLE // Mask XSCL = NOT MASKED // LCDE = NOT ENABLED // Gray Scale = 16 Gray Shades (4 bits/pixel) // LCD Data Width = 8 bit data transfer // Memory Interface = 16 bits // RAMS = Addressing for 8Kx8 SRAM // val = 0x8C; if (PanelType == TYPE_DUAL) { val |= 0x40; // Set panel type to DUAL val &= ~0x04; // Set LCD Data Width to 4 bit data transfer } WriteRegister(1, val); // Write to Mode Register //-------------------------------------// // Line Byte/Word Count Register // SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 49 // Bits 0-7 are in AUX[2], Bit 8 is in AUX[3]. // // Because the Memory Interface is set to 16 bits, the // Line Byte/Word Count Register counts in words. In addition, // there are 2 pixels/byte since there are 16 gray levels. // To calculate the number of words in a scan line, use the following // formula: // // number of pixels per scan line // -------------------------------- - 1 // (2 pixels/byte) * (2 bytes/word) // val = (PanelX / 4) - 1; // For 16 gray shades only WriteRegister(2, val & 0xff); WriteRegister(3, (val >> 8) & 0x01); // Line Byte/Word Count Register // Line Byte/Word Count/Power Save Reg // // BytesPerScanLine is a global variable // BytesPerScanLine = (PanelX / 2); // For 16 gray shades only //-------------------------------------// // // // // // // Total Display Line Count Register Screen 1 Display Line Count Register To show a full image on Screen 1, copy the Total Display Line Count into the Screen 1 Display Line Count. // // Assume that all panels smaller than 400 lines are in 4 bit mode // if (PanelY < 400) { val = ReadRegister(1); val &= ~0x04; WriteRegister(1, val); // Write to Mode Register; LCD Data Width = 4 bits } val = PanelY; // // // // // if A dual panel LCD will, of course, have two panels. Each panel will show either the top or bottom half of the image, which is half of the vertical resolution. (PanelType == TYPE_DUAL) val /= 2; Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 50 Epson Research and Development Vancouver Design Center --val; WriteRegister(4, val & 0xff); // Write to Total Display Line Count Reg WriteRegister(0x0a, val & 0xff); // Write to Screen 1 Display Line Count Reg WriteRegister(5, (val >> 8) & 0x03); // Total Disp Line Cnt (MSB)/WF Count Reg WriteRegister(0x0b, (val >> 8) & 0x03); // Scrn 1 Disp Line Count Reg (MSB) //-------------------------------------// // Set Screen 1 Display Start Address to beginning of video memory // WriteRegister(6, 0); // Write to Screen 1 Display Start Address Register WriteRegister(7, 0); //-------------------------------------// // // // // // if Screen 2 Display Start Address Register If using a dual panel, the Screen 2 Display Start Address must point to the second half of the image in video memory. (PanelType == TYPE_DUAL) { val = (unsigned int) ((ReadRegister(3) & 0x01) << 8) | ReadRegister(2); ++val; val *= (PanelY / 2); WriteRegister(8, val & 0xff); WriteRegister(9, val >> 8); } else { // // On a single panel, Screen 1 was programmed to show all of its // lines. Consequently Screen 2 will not be seen, and so the // Screen 2 Display Start Address will have no observable effect. // For convenience, set the screen 2 address to 0. // WriteRegister(8, 0); WriteRegister(9, 0); } //-------------------------------------// // // // // // // When the SDU1352B0x is set to 64k, video memory exists from D000:0000 to D000:FFFF. When the SDU1352B0x is set to 128k, video memory exists from C000:0000 to D000:FFFF. As far as the SED1352 is concerned, video memory ALWAYS begins at C000:0000, even if there is no physical memory present. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 51 // Since this demo program uses only 64k, the Display Start Address // Registers must be adjusted to point to the D000 segment. To do so, // note that these registers refer to words of data, not bytes, // since the Memory Interface is set to 16 bits. Consequently adding // the value 8000h (words) to the address registers will effectively // add 10000h (bytes) to the address. Adding 10000h to C000:0000 will // point to D000:0000, which is why this address correction works. // WriteRegister(7, 0x80); // MSB of Screen 1 Display Start Address val = ReadRegister(9); val += 0x80; WriteRegister(9, val); // MSB of Screen 2 Display Start Address //-------------------------------------// // Set Address Pitch Adjustment to 0 // WriteRegister(0x0d, 0); // Write to Address Pitch Adjustment Register //-------------------------------------// // Update Look-Up Table for 16 gray shades // for (x = 0; x < 16; ++x) { WriteRegister(0x0e, x); WriteRegister(0x0f, x); } //-------------------------------------// // Now that system is initialized, enable LCDE // val = ReadRegister(1); val |= 0x10; // LCDE enabled WriteRegister(1, val); } Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 52 Epson Research and Development Vancouver Design Center 6.3 Advanced Functions #define VIRTUAL_X #define VIRTUAL_Y (360) (360) //------------------------------------------------------------------------// // FUNCTION: ShowRegisters() // // DESCRIPTION: Shows the contents of the SED1352 registers. // // INPUTS: None. // RETURN VALUE: None. // //------------------------------------------------------------------------void ShowRegisters(void) { static unsigned char x; printf("SED1352 Registers: "); for (x = 0; x < 16; ++x) printf("%02X ", ReadRegister(x)); printf("\nSED1352 Look-Up Table: "); for (x = 0; x < 16; ++x) { WriteRegister(0x0e, x); printf("%02X ", ReadRegister(0x0f)); } ShowMenu(); } //------------------------------------------------------------------------// // FUNCTION: GrayShadeBars() // // DESCRIPTION: Displays one set of vertical bars, each with a // different gray shade. // // INPUTS: None. // // RETURN VALUE: None. // //------------------------------------------------------------------------void GrayShadeBars(void) { static unsigned int val, x; static unsigned char _far *pVideo; SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 53 Initialize(); ClearLCDScreen(); // // For 64k only // FP_SEG(pVideo) = 0xd000; FP_OFF(pVideo) = 0x0000; // // Update Look-Up Table for 16 gray shades // for (x = 0; x < 16; ++x) { WriteRegister(0x0e, x); WriteRegister(0x0f, x); } // // Change Mode Register for 16 gray shades // val = ReadRegister(1); val |= 0x08; WriteRegister(1, val); // // Update Line Byte Count register for 16 gray shades // // Since 16 gray shades corresponds to 2 pixels per byte, there // are ((x horizontal pixels)/2) bytes per scan line. This means that // there are ((x horizontal pixels)/4) words per scan line. // // Since the Memory Interface is set to 16 bits, the Line Byte/Word Count // refers to words. // val = (PanelX / 4) - 1; BytesPerScanLine = (PanelX / 2); WriteRegister(2, val & 0xff); WriteRegister(3, (val >> 8) & 0x01); PanelGrayLevel = 16; ShowVerticalBars(pVideo); // // Show text. The lightest gray shade is set to PanelGrayLevel-1. // ShowText(pVideo, "VERTICAL BARS AT SIXTEEN GRAY SHADES", PanelGrayLevel-1); } // Line Byte Count Register // Line Byte Count/Power Save Reg Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 54 Epson Research and Development Vancouver Design Center //------------------------------------------------------------------------// // FUNCTION: ShowVerticalBars() // // DESCRIPTION: Displays a series of vertical bars, each with a // different gray shade. For 4 gray levels, each // vertical bar is 40 pixels wide. For 16 gray levels, // each vertical bar is 20 pixels wide. // // INPUTS: Video address which points to beginning of vertical bars. // This address must be at the leftmost column of the display. // // RETURN VALUE: None. // //------------------------------------------------------------------------void ShowVerticalBars(unsigned char _far *pVideo) { static unsigned int y; static unsigned int Bar, BarWidth, val; static unsigned char _far *pVideoStart; // // To display vertical bars, this routine assumes that pVideo points // to the beginning of a scan line. In addition, this routine assumes that // the Address Pitch Adjustment Register is 0 (no virtual display). // To write one vertical line, first write one pixel to the first byte // pointed to by pVideo. Write the next pixel to the byte on the next scan // line pointed to by pVideo+BytesPerScanLine (this only works if the // Address Pitch Adjustment Register is 0). Continue writing pixels by // going down each scan line. // pVideoStart = pVideo; for (y = 0; y < PanelY; ++y) { for (Bar = 0; Bar < PanelGrayLevel; ++Bar) { for (BarWidth = 0; BarWidth < 10; ++BarWidth) { if (PanelGrayLevel == 4) { // // In the 4 gray level mode, each pixel is stored as two bits. // Since a byte holds 8 bits, there are 4 pixels per byte. // The variable "val" represents the pixel value. // val = Bar % 4; *pVideo++ = (unsigned char) ((val << 6) | (val << 4) | (val << 2) | val); } else { SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 55 // // In the 16 gray level mode, each pixel is stored as four bits. // Since a byte holds 8 bits, there are 2 pixels per byte. // The variable "val" represents the pixel value. // val = Bar % 16; *pVideo++ = (unsigned char) ((val << 4) | val); } } } // // Point to the beginning of the next scan line // pVideoStart += BytesPerScanLine; pVideo = pVideoStart; } } //------------------------------------------------------------------------// // ShowText() // // DESCRIPTION: Writes text to the LCD panel. Text must only contain // the letters A-Z, and the space character. All other // characters are replaced by spaces. // // NOTES: It is assumed that a pixel set to a value of 0 represents the // background color (black). // The character "!" is translated to a block character. // //------------------------------------------------------------------------void ShowText(unsigned char _far *pdisplayStart, char *str, int color) { static const unsigned char *pFont; static unsigned char _far *pdisplayFirstColumn; static unsigned char _far *pDisplay; static unsigned char ch; static unsigned int y, val, Display; // // Each letter in the font is 8 x 8 bits // static const unsigned char font[28][8] = { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, { 0x30, 0x78, 0xCC, 0xCC, 0xFC, 0xCC, { 0xFC, 0x66, 0x66, 0x7C, 0x66, 0x66, { 0x3C, 0x66, 0xC0, 0xC0, 0xC0, 0x66, 0x00, 0xFF, 0xCC, 0xFC, 0x3C, 0x00 0xFF 0x00 0x00 0x00 }, }, }, }, }, // // // // // blank block char A B C Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 56 Epson Research and Development Vancouver Design Center { { { { { { { { { { { { { { { { { { { { { { { 0xF8, 0xFE, 0xFE, 0x3C, 0xCC, 0x78, 0x1E, 0xE6, 0xF0, 0xC6, 0xC6, 0x38, 0xFC, 0x78, 0xFC, 0x78, 0xFC, 0xCC, 0xCC, 0xC6, 0xC6, 0xCC, 0xFE, 0x6C, 0x62, 0x62, 0x66, 0xCC, 0x30, 0x0C, 0x66, 0x60, 0xEE, 0xE6, 0x6C, 0x66, 0xCC, 0x66, 0xCC, 0xB4, 0xCC, 0xCC, 0xC6, 0xC6, 0xCC, 0xC6, 0x66, 0x68, 0x68, 0xC0, 0xCC, 0x30, 0x0C, 0x6C, 0x60, 0xFE, 0xF6, 0xC6, 0x66, 0xCC, 0x66, 0xE0, 0x30, 0xCC, 0xCC, 0xC6, 0x6C, 0xCC, 0x8C, 0x66, 0x78, 0x78, 0xC0, 0xFC, 0x30, 0x0C, 0x78, 0x60, 0xFE, 0xDE, 0xC6, 0x7C, 0xCC, 0x7C, 0x70, 0x30, 0xCC, 0xCC, 0xD6, 0x38, 0x78, 0x18, 0x66, 0x68, 0x68, 0xCE, 0xCC, 0x30, 0xCC, 0x6C, 0x62, 0xD6, 0xCE, 0xC6, 0x60, 0xDC, 0x6C, 0x1C, 0x30, 0xCC, 0xCC, 0xFE, 0x38, 0x30, 0x32, 0x6C, 0x62, 0x60, 0x66, 0xCC, 0x30, 0xCC, 0x66, 0x66, 0xC6, 0xC6, 0x6C, 0x60, 0x78, 0x66, 0xCC, 0x30, 0xCC, 0x78, 0xEE, 0x6C, 0x30, 0x66, 0xF8, 0xFE, 0xF0, 0x3E, 0xCC, 0x78, 0x78, 0xE6, 0xFE, 0xC6, 0xC6, 0x38, 0xF0, 0x1C, 0xE6, 0x78, 0x78, 0xFC, 0x30, 0xC6, 0xC6, 0x78, 0xFE, 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 }, }, }, }, }, }, }, }, }, }, }, }, }, }, }, }, }, }, }, }, }, }, } }; // // // // // // // // // // // // // // // // // // // // // // // D E F G H I J K L M N O P Q R S T U V W X Y Z pdisplayFirstColumn = pdisplayStart; pDisplay = pdisplayFirstColumn; // // If there are 4 gray levels, there are 4 pixels/byte // if (PanelGrayLevel == 4) { color &= 0x03; while (*str != 0) { ch = *str++; if (ch == '!') pFont = &font[1][0]; // "Block" character else if ((ch < 'A') || (ch > 'Z')) pFont = &font[0][0]; // blank character else pFont = &font[ch - 'A' + 2][0]; for (y = 0; y < 8; ++y) { pDisplay = pdisplayFirstColumn; val = *pFont++; // // Since there are 4 gray shades, each bit in the font will be // represented in display memory as a two bit gray shade. SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 57 // if (val & 0x80) Display = color << 6; else Display = 0; if (val & 0x40) Display |= (color << 4); if (val & 0x20) Display |= (color << 2); if (val & 0x10) Display |= color; *pDisplay++ = (unsigned char) Display; if (val & 0x08) Display = color << 6; else Display = 0; if (val & 0x04) Display |= (color << 4); if (val & 0x02) Display |= (color << 2); if (val & 0x01) Display |= color; *pDisplay++ = (unsigned char) Display; pdisplayFirstColumn += BytesPerScanLine; } pdisplayStart += 2; // Point to next character pdisplayFirstColumn = pdisplayStart; } } else // { color while { ch if 16 Gray Shades &= 0x0f; (*str != 0) = *str++; (ch == '!') // "Block" character pFont = &font[1][0]; else if ((ch < 'A') || (ch > 'Z')) pFont = &font[0][0]; else pFont = &font[ch - 'A' + 2][0]; for (y = 0; y < 8; ++y) { pDisplay = pdisplayFirstColumn; val = *pFont++; // // Since there are 16 gray shades, each bit in the font will be // represented in display memory as a four bit gray shade. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 58 Epson Research and Development Vancouver Design Center // if (val & 0x80) Display = color << 4; else Display = 0; if (val & 0x40) Display |= color; *pDisplay++ = (unsigned char) Display; if (val & 0x20) Display = color << 4; else Display = 0; if (val & 0x10) Display |= color; *pDisplay++ = (unsigned char) Display; if (val & 0x08) Display = color << 4; else Display = 0; if (val & 0x04) Display |= color; *pDisplay++ = (unsigned char) Display; if (val & 0x02) Display = color << 4; else Display = 0; if (val & 0x01) Display |= color; *pDisplay++ = (unsigned char) Display; pdisplayFirstColumn += BytesPerScanLine; } pdisplayStart += 4; // Point to next character pdisplayFirstColumn = pdisplayStart; } } } //------------------------------------------------------------------------// // FUNCTION: SplitScreen() // // DESCRIPTION: Show split screen. // // INPUTS: None. // RETURN VALUE: None. // //------------------------------------------------------------------------void SplitScreen(void) { SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 59 static static static static static static static unsigned unsigned unsigned unsigned unsigned unsigned unsigned char _far *pVideoImage1; char _far *pVideoImage2; long ImageSize; int OriginalLineCount; int val; int MinLineCount; int MaxVirtualScanLines; Initialize(); ClearLCDScreen(); // // For 64k only // FP_SEG(pVideoImage1) = 0xd000; FP_OFF(pVideoImage1) = 0x0000; // // Calculate starting video memory location for image 2 by finding the // last location of image 1 // ImageSize = BytesPerScanLine * PanelY; // // Because the image size is limited to a maximum of 320 x 240, and there // is 64k of video memory, there is enough memory available. // FP_SEG(pVideoImage2) = 0xd000; FP_OFF(pVideoImage2) = (unsigned int) ImageSize; ShowVerticalBars(pVideoImage1); ShowHorizontalBars(pVideoImage2); // // Show text. The lightest gray shade is set to PanelGrayLevel-1. // ShowText(pVideoImage1, "SPLIT SCREEN IMAGE ONE", PanelGrayLevel-1); ShowText(pVideoImage2, "SPLIT SCREEN IMAGE TWO", PanelGrayLevel-1); // // Set Screen 2 Display Start Address register to point to Image 2 // // Adjust ImageSize to represent the size in words, not bytes. // This is because the Memory Interface is set to 16 bits. // val = (unsigned int) ImageSize / 2; val += 0x8000; // Point to D000 segment instead of C000 segment Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 60 Epson Research and Development Vancouver Design Center WriteRegister(8, (unsigned int) val & 0xff); WriteRegister(9, (unsigned int) val >> 8); // // // // // if If this is a dual panel, then the split screen has just been shown. Otherwise, set up the Screen 1 Display Line Count register for single panels. (PanelType == TYPE_SINGLE) { OriginalLineCount = (unsigned int) ((ReadRegister(0x0b) & 0x03) << 8) | ReadRegister(0x0a); // Only for 64k of memory MaxVirtualScanLines = (unsigned int) ((unsigned long) 0x10000 / BytesPerScanLine); MinLineCount = OriginalLineCount (MaxVirtualScanLines - OriginalLineCount) + 1; Delay(0, 5); // // Scroll image 2 down // for (val = MinLineCount; val < OriginalLineCount; val += 1) { WriteRegister(0x0a, val & 0xff); // Total Display Line Count WriteRegister(0x0b, (val >> 8) & 0x03); // Total Disp Line Cnt/WF Count Delay(0, 1); } // // Scroll image 2 up // for (val = OriginalLineCount; val > MinLineCount; val -= 1) { WriteRegister(0x0a, val & 0xff); // Total Display Line Count WriteRegister(0x0b, (val >> 8) & 0x03); // Total Disp Line Cnt/WF Count Delay(0, 1); } val = MinLineCount; WriteRegister(0x0a, val & 0xff); WriteRegister(0x0b, (val >> 8) & 0x03); Delay(0, 5); } } // Total Display Line Count Reg // Total Disp Line Cnt/WF Count SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 61 void SetStartAddress(int x, int y) { int addr; // // Assume 16 gray shades // addr = 0x8000 + (x/2 + (VIRTUAL_X/2) * y)/2; WriteRegister(6, addr & 0xff); WriteRegister(7, addr >> 8); } void PanScroll(void) { static unsigned int x, y; static unsigned int MaxX, MaxY; static unsigned int val, pitch; static unsigned char _far *pVideo; printf("Showing Panning and Scrolling\n"); Initialize(); ClearLCDScreen(); // // This pitch is calculated for 16 gray shades // pitch = ((VIRTUAL_X / 2) - BytesPerScanLine) / 2; WriteRegister(0x0d, pitch); BytesPerScanLine = (VIRTUAL_X / 2); // // For 64k only // FP_SEG(pVideo) = 0xd000; FP_OFF(pVideo) = 0x0000; // // Display random blocks of data. To do so, a text character will be used. // This character sets all pixels in a character region, so a block is // shown at the specified gray shade. // // Seed the random number generator with current time srand((unsigned) time(NULL)); Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 62 Epson Research and Development Vancouver Design Center for (x = 0; x < 300; ++x) { FP_OFF(pVideo) = (unsigned int) ((rand() * 0xffffL) / RAND_MAX); val = rand() % 50; ShowText(pVideo, "!", rand() % 16); } ShowBorders(); // // Move virtual display from (0, 0) to (MaxX, 0) // MaxX = VIRTUAL_X - PanelX; MaxY = VIRTUAL_Y - PanelY; for (x = 0; x <= MaxX; ++x) { SetStartAddress(x, 0); Delay(0, 1); } for (y = 0; y <= MaxY; ++y) { SetStartAddress(MaxX, y); Delay(0, 1); } for (x = MaxX; x > 0; --x) { SetStartAddress(x, MaxY); Delay(0, 1); } for (y = MaxY; y > 0; --y) { SetStartAddress(0, y); Delay(0, 1); } SetStartAddress(0, 0); } //------------------------------------------------------------------------// // FUNCTION: PowerSaving() // // DESCRIPTION: Starts power saving mode 2. // // INPUTS: None. // RETURN VALUE: None. // SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 63 //------------------------------------------------------------------------void PowerSaving(void) { static unsigned int val; printf("Starting Power Saving\n"); val = ReadRegister(3); val &= 0x3f; val |= 0x80; WriteRegister(3, val); // Set power saving mode 2 printf("Press any key to cancel power saving\n"); getch(); val &= 0x38; WriteRegister(3, val); } // Cancel power saving mode 2 //------------------------------------------------------------------------// // FUNCTION: PowerSaving() // // DESCRIPTION: Starts power saving mode 2. // // INPUTS: None. // RETURN VALUE: None. // //This is an optional method of power saving. // //------------------------------------------------------------------------void PowerSaving(void) { static unsigned int val; printf("Starting Power Saving\n"); // // The following are the steps to enter a power save mode. // // // Step 1: Turn off display // val = ReadRegister(1); val &= 0x7f; WriteRegister(1, val); // // Step 2: Disable LCDE (turn off LCD power supply). // For the SDU1353B0C, set LCDE bit to 0. // val = ReadRegister(1); val &= 0xef; WriteRegister(1, val); // Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 64 Epson Research and Development Vancouver Design Center // Step 2: Wait for LCD power supply to drop to zero volts // For the SDU1353B0C, wait about a half second. // Delay(500); // // Step 3: Enter Power Save Mode // val = ReadRegister(3); val &= 0x3f; val |= 0x80; WriteRegister(3, val); // Set power saving mode 2 printf("Press any key to cancel power saving\n"); getch(); // // The following are the steps to exit a power save mode. // // // Step 1: Exit Power Save Mode // val = ReadRegister(3); val &= 0x3f; WriteRegister(3, val); // Cancel power saving mode 2 // // Step 2: Enable LCDE (turn on LCD power supply). // For the SDU1353B0C, set LCDE bit to 1. // val = ReadRegister(1); val |= 0x10; WriteRegister(1, val); // // Step 3: Turn on display. // val = ReadRegister(1); val |= 0x80; WriteRegister(1, val); ShowMenu(); } SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 65 7 GLOSSARY 1352 display memory gray shade LCD LCD controller LUT panel panning pixel power saving register scrolling SED1352 SDU1352B0x viewport virtual display The SED1352 LCD controller chip. Memory in which an image is stored for display by the SED1352. A specific combination of white and black colors. For example, a lighter gray shade has more white than black. Liquid Crystal Display. The display device used by the SED1352. The device used to control the LCD display. The SED1352 is an LCD controller. Look-Up Table, or palette. The LUT treats the value of a pixel as an index into an array of gray shades. The circuitry and viewable area of an LCD display which supports a single image. LCD displays may have one or two panels. The right or left movement of the viewport in a virtual display. Picture Element. A pixel is seen as a dot on the display, and can be shown using one of several different gray shades. Combining pixels in a group creates an image. A means of reducing the power consumption of the SED1352. A memory storage location to control a peripheral, such as the SED1352. The up and down movement of the viewport in a virtual display. The 1352 chip. The evaluation board for the SED1352. The SDU1352B0x is an ISA board for a PCcompatible computer. The visible portion of a virtual display. An image stored in display memory that is larger than what the LCD display can show. A virtual display supports panning and scrolling. Programming Notes and Examples Issue Date: 98/10/08 SED1352 X16-BG-007-04 Page 66 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-BG-007-04 Programming Notes and Examples Issue Date: 98/10/08 SED1352 Dot Matrix Graphics LCD Controller 1352SHOW.EXE Display Utility Document Number: X16-UI-001-08 Copyright (c) 1995, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-UI-001-08 1352SHOW.EXE Display Utility Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 1352SHOW.EXE DISPLAY UTILITY 1352SHOW is an OEM demonstration utility used to load and display GIF images. It can also be used to demonstrate the split screen capabilities of the SED1352 by loading two images and vertically scrolling one image. Program Requirements Video Controller Display Type BIOS DOS Program DOS Version Windows Program Windows DOS Box Windows DOS Full Screen OS/2 DOS Full Screen : SED1352 : Up to 640x480 LCD : Seiko Epson BIOS1352 version 1.11 or later : Yes : 3.0 or greater : No : Yes : Yes : Yes Installation Copy the file 1352show.exe to a directory that is in the DOS path on your hard drive. Usage 1352SHOW is invoked from the DOS command line as follows. 1352show [image1] [image2] [/i] [/?] Where: image1 image2 /i /? is the first screen image to be displayed. is the second screen image to be displayed. will invert all displayed images (show as negative). produces the usage message. with no arguments will run the program in split screen mode. This will display two predefined images, with screen one displaying horizontal bars and screen two displaying vertical bars. Screen two may be scrolled up and down using the arrow, page up, page down, home and end keys. displays the named GIF image. displays the two named GIF images in a split screen. Screen two may be scrolled up and down using the arrow, page up, page down, home and end keys. Examples: 1352show 1352show picture1.gif 1352show dog.gif cat.gif Pressing the ESC key will terminate the program. 1352SHOW.EXE Display Utility Issue Date: 98/10/08 SED1352 X16-UI-001-08 Page 4 Epson Research and Development Vancouver Design Center Comments * * * * * * 1352SHOW requires BIOS1352.COM to be loaded prior to running. Split screen viewing is only allowed on single panels. The size of screen two is determined by available memory and number of gray shades. If there is insufficient memory for screen two 1352SHOW will not accept the two image files and will generate an error message. When loading two GIF images, it may take several seconds of apparent inactivity to load the second image into memory. The GIF format must be 16 color, non-interlaced GIF89a format. 1352SHOW will clear the screen when the Esc key is pressed. Program Messages ERROR: Split screen available for single panel only. Split screen viewing is only allowed on single panels. ERROR: This program requires BIOS1352 to be loaded! The program BIOS1352.COM must be run before 1352SHOW. Load BIOS1352.COM and re-run 1352SHOW.EXE. File "filename" not found or cannot be opened for reading. The GIF file you are trying to display is not in your DOS path or not on your system. File is not GIF89a format. The GIF file contains an invalid format. 1352SHOW only supports GIF89a format. Insufficient video memory for second image. There is not enough video memory available to store both images. Invalid format in the GIF file. Use non-interlaced GIF89a format. SED1352 X16-UI-001-08 1352SHOW.EXE Display Utility Issue Date: 98/10/08 SED1352 Dot Matrix Graphics LCD Controller VIRTUAL.EXE Display Utility Document Number: X16-UI-002-08 Copyright (c) 1995, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-UI-002-08 VIRTUAL.EXE Display Utility Issue Date: 08/10/08 Epson Research and Development Vancouver Design Center Page 3 VIRTUAL.EXE DISPLAY UTILITY VIRTUAL.EXE demonstrates the virtual panning capabilities of the SED1352. An image larger than the display resolution is loaded in display memory. VIRTUAL.EXE will then display a portion of the complete image while providing panning capabilities using the arrow keys for navigation. Program Requirements Video Controller Display Type BIOS DOS Program DOS Version Windows Program Windows DOS Box Windows DOS Full Screen OS/2 DOS Full Screen : SED1352 : Up to 640x480 LCD : Seiko Epson BIOS1352 version 1.11 or later : Yes : 3.0 or greater : No : Yes : Yes : Yes Installation Copy the file virtual.exe to a directory that is in the DOS path on your hard drive. Usage VIRTUAL is invoked from the DOS command line as follows. virtual [x=n] [y=n] [/?] Where: x y /? is the horizontal resolution (in multiples of 8). is the vertical resolution. produces a usage message. If the user does not provide the virtual size, the program will automatically select the size based on memory and panel size. The user can then navigate throughout the image using the arrow keys to pan and scroll the screen. Pressing the ESC key terminates the program. Comments * * VIRTUAL requires BIOS1352.COM to be loaded prior to running. VIRTUAL forces four gray shade mode regardless of original BIOS1352 settings. The original BIOS1352 settings are restored on exiting VIRTUAL. VIRTUAL.EXE Display Utility Issue Date: 08/10/08 SED1352 X16-UI-002-08 Page 4 Epson Research and Development Vancouver Design Center Program Messages ERROR: This program requires BIOS1352 to be loaded! The program BIOS1352.COM must be run before VIRTUAL.EXE. Load BIOS1352.COM and then re-run VIRTUAL.EXE. ERROR: Insufficient memory for virtual display. The virtual display is too large to fit in memory. Choose a smaller x or y value. ERROR: Horizontal resolution must be a multiple of 8. Panning moves in multiples of pixels. Choose a horizontal resolution which is a multiple of 8, so panning will not suffer from screen wrap-around. ERROR: Specified horizontal resolution is smaller than panel resolution. The virtual display must always be larger than the panel size. ERROR: Specified vertical resolution is smaller than panel resolution. The virtual display must always be larger than the panel size. SED1352 X16-UI-002-08 VIRTUAL.EXE Display Utility Issue Date: 08/10/08 SED1352 Dot Matrix Graphics LCD Controller BIOS1352.COM Utility Document Number: X16-UI-003-08 Copyright (c) 1995, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-UI-003-08 BIOS1352.COM Utility Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 BIOS1352.COM UTILITY BIOS1352 is a DOS Terminate and Stay Resident (TSR) program which replaces and/or supplements the PC video interrupt INT 10h. This program provides text, scroll, and cursor functionality when no VGA BIOS is present. Although the SED1352 is not a VGA or EGA compatible controller, this program is supplied to give the user a familiar prompt. Within limits BIOS1352 simulates a VGA BIOS and will allow standard output functions to work. DOS programs such as Edlin, Format, Debug, and internal commands such as Copy, Ren, Mkdir, etc., should work; however, complex programs such as Edit, Qbasic, and Scandisk will not work. The standard output functions are handled by the VGA BIOS, if present. Program Requirements Video Controller Display Type BIOS DOS Program DOS Version Windows Program Windows DOS Box Windows DOS Full Screen OS/2 DOS Full Screen : SED1352 : Up to 640x480 LCD : None or any VGA : Yes : 3.0 or greater : No : Yes : Yes : Yes Installation Copy the file bios1352.com to a directory that is in the DOS path on your hard drive. Usage BIOS1352.COM is run from the DOS command line as follows: bios1352 type x=n y=n g=n p=n m=n [/?] Where: type x y g p m /? is the panel type: single for single panel or dual for dual panel is the horizontal panel size in pixels (decimal) is the vertical panel size in lines (decimal) is the number of gray shades: 4 or 16 is the port address in hex: 300|310...360|370 is the memory size in K bytes: 64 or 128 produces a usage message The order and case of arguments is arbitrary. Any invalid or missing argument will result in an error message. Note that the port address must be the same as the physical address set on the SDU1352 evaluation board. Example: BIOS1352 SINGLE x=320 y=240 g=16 p=320 m=128 BIOS1352.COM Utility Issue Date: 98/10/08 SED1352 X16-UI-003-08 Page 4 Epson Research and Development Vancouver Design Center Comments * BIOS1352 can be used in conjunction with a Monochrome Display Adapter (mono) card. The standard DOS command MODE MONO will switch to the mono card and the DOS command MODE CO80 will switch to the LCD panel. BIOS1352 emulates mode 3, but any program that attempts to write directly to video memory, bypassing the video BIOS, will not display correctly. BIOS1352 can be used in conjunction with a VGA BIOS. In this case all TTY output will be displayed on the VGA monitor. When the SED1352 video memory is specified as 64K bytes, the SED1352 video memory will reside at D000h to DFFFh. For 128K bytes of SED1352 video memory, the memory will reside at C000h to DFFFh. * * * Program Messages ERROR: Panels greater than 640 pixels not supported. More than 640 horizontal pixels has been specified for the panel in the command line. ERROR: Panels greater than 480 lines not supported. More than 480 vertical lines has been specified for the panel in the command line. ERROR: Invalid port specified. The port address (p) must be specified in the format 3x0 in the command line. The range is 300h to 370h in 10h increments. ERROR: Only 4 or 16 gray shades allowed. A number other than 4 or 16 has been specified for the variable g in the command line. ERROR: Not enough video memory for the panel. The panel specified is too large to run in 16 gray shades mode. Select 4 gray shades instead. ERROR: Video memory and VGA BIOS memory conflict. Both the SED1352 video memory and the VGA BIOS are trying to use the memory at location C000h to CFFFh. ERROR: Only 8k, 16k, 32k, 40k, 64k or 128k memory allowed. An invalid value has been specified for memory size (m) on the command line. ERROR: Only 8 or 16 bits allowed for width. The SED1352 only supports 8 or 16 bit memory width. ERROR: Memory size cannot support memory width. Choose one of the following combinations: Memory Size (m) Memory Width (w) 8 8 16 16 32 8 40 8 64 16 128 16 SED1352 X16-UI-003-08 BIOS1352.COM Utility Issue Date: 98/10/08 SED1352 Dot Matrix Graphics LCD Controller 1352GRAY.EXE Display Utility Document Number: X16-UI-004-08 Copyright (c) 1995, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-UI-004-08 1352GRAY.EXE Display Utility Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 1352GRAY.EXE DISPLAY UTILITY 1352GRAY is a menu driven display utility for the SED1352 which demonstrates the gray shades and available palettes. For 128K bytes of display memory and a panel size of 640x400 or less, either 4 or 16 gray shades are available. If the panel size is greater than 640x400 only 4 shades of gray are available. For 64K bytes of display memory and a panel size of 640x200, 320x240 or less, either 4 or 16 shades are available. In 4 gray shade mode it is possible to select 1 of 4 palettes. Program Requirements Video Controller Display Type BIOS DOS Program DOS Version Windows Program Windows DOS Box Windows DOS Full Screen OS/2 DOS Full Screen : SED1352 : Up to 640x480 LCD : Seiko Epson BIOS1352 version 1.11 or later : Yes : 3.0 or greater : No : Yes : Yes : Yes Installation Copy the file 1352gray.exe to a directory that is in the DOS path on your hard drive. Usage 1352GRAY is invoked from the DOS command line as follows. 1352gray [/?] Where: /? produces a usage message. 1352GRAY displays a default gray shade pattern as a series of vertical or horizontal bars. The pattern, number of gray shades, and current palette may be modified by the user when possible. Instructions to modify these options will appear when available. Pressing the ESC key terminates the program and restores the original BIOS1352 settings. 1352GRAY.EXE Display Utility Issue Date: 98/10/08 SED1352 X16-UI-004-08 Page 4 Epson Research and Development Vancouver Design Center Comments * * 1352GRAY requires BIOS1352.COM to be loaded prior to running. Four gray shades is always possible. Switching to 16 gray shades may not be possible if the panel size exceeds 640x400. Program Messages ERROR: This program requires BIOS1352 to be loaded! The program BIOS1352.COM must be run before 1352GRAY. Load BIOS1352.COM and then re-run 1352GRAY.EXE. SED1352 X16-UI-004-08 1352GRAY.EXE Display Utility Issue Date: 98/10/08 SED1352 Dot Matrix Graphics LCD Controller 1352PD.EXE Power Down Utility Document Number: X16-UI-005-07 Copyright (c) 1996, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-UI-005-07 1352PD.EXE Power Down Utility Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 1352PD.EXE POWER DOWN UTILITY 1352PD is an OEM utility program for setting power down modes in the SED1352 LCD Display Controller. It provides a simple method for setting power modes during power consumption testing. Program Requirements Video Controller Display Type BIOS DOS Program DOS Version Windows Program Windows DOS Box Windows DOS Full Screen OS/2 DOS Full Screen : SED1352 : Up to 640x480 LCD : Seiko Epson BIOS1352 version 1.11 or later : Yes : 3.0 or greater : No : Yes : Yes : Yes Installation Copy the file 1352pd.exe to a directory that is in the DOS path on your hard drive. Usage 1352PD is run from the DOS command line as follows: 1352pd ModeNumber Where: ModeNumber is a decimal number (0, 1, or 2) for the desired power down mode. Example: typing the following command line activates power down mode 2: 1352pd 2 1352PD.EXE Power Down Utility Issue Date: 98/10/08 SED1352 X16-UI-005-07 Page 4 Epson Research and Development Vancouver Design Center Comments * * 1352PD.EXE requires BIOS1352.COM to be loaded prior to running. The following power modes are supported: Mode 0 Mode 0 operates at full power. Mode 1 or 2 SED1352 will engage power down mode 1 or 2. SED1352 LUT will be disabled and all LCD signals are forced low. Program Messages Power Down Mode xx is set. The power down mode xx has been set. This message may not be visible if the active display controller is the SED1352. ERROR: Cannot set power mode xx! 1352PD.EXE cannot set the power down mode requested . The power down mode must be 0, 1, or 2. ERROR: This program requires BIOS1352 to be loaded! The program BIOS1352.COM must be run before 1352PD. Load BIOS1352 and re-run 1352PD.EXE. SED1352 X16-UI-005-07 1352PD.EXE Power Down Utility Issue Date: 98/10/08 SED1352 Dot Matrix Graphics LCD Controller 1352READ.EXE Diagnostic Utility Document Number: X16-UI-006-06 Copyright (c) 1996, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-UI-006-06 1352READ.EXE Diagnostic Utility Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 1352READ.EXE DIAGNOSTIC UTILITY 1352READ is an OEM utility program which enables the user to read the SED1352 register contents. It is a useful utility for OEMs wishing to submit a problem report for the video controller. If run with BIOS1352 loaded, it will try to interpret the BIOS settings. Program Requirements Video Controller Display Type BIOS DOS Program DOS Version Windows Program Windows DOS Box OS/2 DOS Full Screen : SED1352 : Up to 640x480 LCD : Seiko Epson BIOS1352.COM (optional) : Yes : 3.0 or greater : No : Yes : Yes Windows DOS Full Screen : Yes Note 1352READ uses "stdout" calls and may be redirected to a file or piped to a DOS filter such as MORE.COM. Installation Copy the file 1352read.exe to a directory that is in the DOS path on your hard drive. Usage From DOS prompt, type the following: 1352read [port] [/?] Where: 1352read port /? without any argument will read the SED1352 registers, including the gray shade lookup table. is the SED1352 port address in hex (e.g., 310). produces a usage message. Example: to generate a report, simply type 1352read [port] > report.txt and the information which 1352READ obtains will be stored in the file report.txt. 1352READ.EXE Diagnostic Utility Issue Date: 98/10/08 SED1352 X16-UI-006-06 Page 4 Epson Research and Development Vancouver Design Center Comments * * It is not necessary to specfy a port address if BIOS1352 has previously been loaded. 1352READ will search for BIOS1352.COM. If this program is found the port address reported by BIOS1352 will be used. If the port address is specified on the 1352READ command line the two port addresses are compared and if different an error message is generated. 1352READ will accept any port address, however, the SDU1352 can only be configured to an address in the range of 300h through 370h. * Program Messages ERROR: 1352 registers not responding at port address [port]. 1352READ has not found an SED1352 at the port address specified. Check the command line port setting for BIOS1352 and/or 1352READ to ensure it is correct and re-run the program. ERROR: 1352READ requires a port address. 1352READ has not detected BIOS1352.COM to obtain the port address and no port address was specified on the command line. Either specify a port address on the 1352READ command line or run BIOS1352.COM prior to running 1352READ. ERROR: BIOS1352 reports a port address of [port], which is different from the specified port address of [port]. The poert address entered for 1352READ is different that the one entered for BIOS1352.COM. Specify the same port address on the 1352READ command line as the one in BIOS1352.COM and the physical address of the SDU1352 evaluation board and re-run the program. WARNING: BIOS1352 state is out of sync with SED1352 registers. One or more of the following command line items reported by BIOS1352 does not match the values found in the SED1352 registers; horizontal panel size, vertical panel size, number of gray shades, or panel type (single or dual). SED1352 X16-UI-006-06 1352READ.EXE Diagnostic Utility Issue Date: 98/10/08 SED1352 Dot Matrix Graphics LCD Controller SDU1352B0C Rev. 1.0 Evaluation Board User Manual Document Number: X16-AN-002-09 Copyright (c) 1995, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-002-09 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 SDU1352B0C REV 1.0 EVALUATION BOARD 1.1 1.2 1.3 . . . . . . . . . . . . . . . . . . . .7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . 8 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.3.9 1.3.10 ISA Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Non-ISA Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SRAM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Monochrome LCD Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . . . . . . . 13 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . . . . . . 14 Crystal Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CPU/Bus Interface Header Strips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Schematic Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Appendix A Appendix B PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SDU1352B0C REV. 1.0 SCHEMATIC DIAGRAMS . . . . . . . . . . . 16 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 SED1352 X16-AN-002-09 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-002-09 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 Epson Research and Development Vancouver Design Center Page 5 List of Tables Table 1-1: Configuration DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 1-2: I/O Mapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 1-3: Decoding Jumper Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 1-4: LCD Signal Connector J1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 1-5: CPU/BUS Connector H1 Pinout Table 1-6: CPU/BUS Connector H2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 List of Figures Figure 1: SDU1352B0C Rev. 1.0 Schematic Diagram (1 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 2: SDU1352B0C Rev. 1.0 Schematic Diagram (2 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 3: SDU1352B0C Rev. 1.0 Schematic Diagram (3 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4: SDU1352B0C Rev. 1.0 Schematic Diagram (4 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 5: SDU1352B0C Rev. 1.0 Schematic Diagram (5 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 6: SDU1352B0C Rev. 1.0 Schematic Diagram (6 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7: SDU1352B0C Rev. 1.0 Schematic Diagram (7 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 SED1352 X16-AN-002-09 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-002-09 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 Epson Research and Development Vancouver Design Center Page 7 1 SDU1352B0C REV 1.0 EVALUATION BOARD This manual reflects the use of the SDU1352B0C Rev 1.0 evaluation board in conjunction with the SED1352 LCD Controller. All appropriate components are surface-mount to reduce cost and minimize board space. 1.1 Features * * * * * * * * * * * * 100 pin QFP5 package SMD technology for all appropriate devices Monochrome STN LCD support 8-bit and 16-bit ISA Bus support 5V operation Two terminal crystal support (up to 25.175MHz) 16-bit wide, 128K bytes SRAM support Configuration Options Support for Software Power Save Modes On-board adjustable LCD BIAS negative power supply On-board adjustable LCD BIAS positive power supply CPU/Bus Interface Header strips SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 SED1352 X16-AN-002-09 Page 8 Epson Research and Development Vancouver Design Center 1.2 Installation and Configuration The SED1352 has 16 configuration inputs (VD[15:0]) which are read on power-up. For the purpose of this design, most of these configuration inputs have been factory set and therefore are not configurable. A four position DIP switch block is provided for the selection of 8- or 16-bit bus interface, and setting I/O address bits 4 through 6. Table 1-1: Configuration DIP Switch Settings Switch SW1-1 SW1-2 SW1-3 SW1-4 SW1-5 SW1-6 SW1-7 SW1-8 Signal VD0 VD1 VD2 VD3 VD7 VD8 VD9 Closed 16-bit ISA Bus interface Direct-mapping I/O M68K CPU Interface Byte-swap high and low data bytes I/O mapping address bit 4 I/O mapping address bit 5 I/O mapping address bit 6 64K bytes of SRAM available at segment D000h Open 8-bit ISA Bus interface Indexing I/O ISA Bus / other MPU other No byte-swap See Table 1-2, "I/O Mapping Example" 128K bytes of SRAM available at segment C000hD000h Note The polarity of the Configuration Dip Switches is Closed = '1' or 'high', Open = '0' or 'low'. Factory set fixed options on this board are: * * 16-bit display memory interface (either 64K bytes or 128K bytes) 128K bytes available at C000h memory segment This board is also pre-set to use indexing I/O with address 0000 0011 0??? 000x, where x is don't care and ??? can be configured with dip-switch SW1-5 through SW1-7. The factory setting of ??? = 001, i.e., I/O address = 0310h and 0311h. When using direct-mapping I/O, the I/O address is 0000 0011 0??? xxxx, where x is don't care and ??? can be configured with dip-switch SW1-5 through SW1-7. If ??? = 001, then the I/O address for AUX[00h ] = 0310h, I/O address for AUX[01h] = 0311h, I/O address for AUX[02h] = 0312h and so on. Table 1-2: I/O Mapping Example I/O Mapping Address (Hex) bit 6 bit 5 bit 4 0 0 1 Table 1-3: Decoding Jumper Setting JP1 JP2 JP3 JP4 Description Set to the same polarity as SW1-1 (VD0) Set to the same polarity as SW1-5 (VD7) Set to the same polarity as SW1-6 (VD8) Set to the same polarity as SW1-7 (VD9) 1-2 1 1 1 1 2-3 0 0 0 0 Note These jumpers are necessary for the external ISA Bus decode logic. SED1352 X16-AN-002-09 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 Epson Research and Development Vancouver Design Center Page 9 LCD Signal Connector Pinout Table 1-4: LCD Signal Connector J1 Pinout SED1352 Pin Name LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 N/C XSCL NC LP YD GRND N/C VLCD VCC +12V VDDH WF LCDENB LCD Connector Pin No. 1 3 5 7 9 11 13 15 17-31 (odd pins) 33 35 37 39 2-26 (even pins) 28 30 32 34 36 38 40 Mono STN LCD 8-bit LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 UD0 UD1 UD2 UD3 4-bit Lower panel display data for dual panel-dual drive mode. In 8-bit single panel-single drive mode, these are the least significant 4 bits of the 8-bit output data to the panel (data[3:0]). In 4-bit single panel mode, these outputs are low. Upper panel display data for dual panel-dual drive mode. In 8-bit single panel-single drive mode, these are the most significant 4 bits of the 8-bit output data to the panel (data[7:4]). In 4-bit single panel mode, these are the 4 data bits output to the panel. Comments XSCL LP YD GRND XSCL LP YD GRND Shift Clock for LCD data Latch Pulse output Vertical Scanning Start Pulse Logic Ground VLCD VLCD +5V +5V +12V +12V VDDH VDDH WF WF /LCDPWR /LCDPWR Negative power supply output (-18V to -23V) Positive power supply output (+23V to +40V) LCD backplane Bias signal LCD power control to external supply SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 SED1352 X16-AN-002-09 Page 10 Epson Research and Development Vancouver Design Center CPU / BUS Interface Connector Pinouts Table 1-5: CPU/BUS Connector H1 Pinout Connector Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CPU/BUS Pin Name SD0 SD1 SD2 SD3 GND GND SD4 SD5 SD6 SD7 GND GND SD8 SD9 SD10 SD11 GND GND SD12 SD13 SD14 SD15 RESET GND GND GND +12V +12V /SBHE /IOSC /MEMCS Comments Connected to DB0 of the SED1352 Connected to DB1 of the SED1352 Connected to DB2 of the SED1352 Connected to DB3 of the SED1352 Ground Ground Connected to DB4 of the SED1352 Connected to DB5 of the SED1352 Connected to DB6 of the SED1352 Connected to DB7 of the SED1352 Ground Ground Connected to DB8 of the SED1352 Connected to DB9 of the SED1352 Connected to DB10 of the SED1352 Connected to DB11 of the SED1352 Ground Ground Connected to DB12 of the SED1352 Connected to DB13 of the SED1352 Connected to DB14 of the SED1352 Connected to DB15 of the SED1352 Connected to the RESET signal of the SED1352 Ground Ground Ground 12 volt supply 12 volt supply Connected to the BHE# signal of the SED1352 Connected to the IOCS# signal of the SED1352 Connected to the MEMCS# signal of the SED1352 IOCHRDY Connected to the READY signal of the SED1352 SED1352 X16-AN-002-09 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 Epson Research and Development Vancouver Design Center Page 11 Table 1-6: CPU/BUS Connector H2 Pinout Connector Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CPU/BUS Pin Name SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 GND GND SA8 SA9 SA10 SA11 SA12 SA13 GND GND SA14 SA15 SA16 SA17 SA18 SA19 GND GND +5V +5V /IOW /IOR /SMEMW /SMEMR Comments Connected to AB0 of the SED1352 Connected to AB1 of the SED1352 Connected to AB2 of the SED1352 Connected to AB3 of the SED1352 Connected to AB4 of the SED1352 Connected to AB5 of the SED1352 Connected to AB6 of the SED1352 Connected to AB7 of the SED1352 Ground Ground Connected to AB8 of the SED1352 Connected to AB9 of the SED1352 Connected to AB10 of the SED1352 Connected to AB11 of the SED1352 Connected to AB12 of the SED1352 Connected to AB13 of the SED1352 Ground Ground Connected to AB14 of the SED1352 Connected to AB14 of the SED1352 Connected to AB16 of the SED1352 Connected to AB17 of the SED1352 Connected to AB18 of the SED1352 Connected to AB19 of the SED1352 Ground Ground 5 volt supply 5 volt supply Connected to the IOW# signal of the SED1352 Connected to the IOR# signal of the SED1352 Connected to the MEMW# signal of the SED1352 Connected to the MEMR# signal of the SED1352 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 SED1352 X16-AN-002-09 Page 12 Epson Research and Development Vancouver Design Center 1.3 Technical Description 1.3.1 ISA Bus Support This board directly supports the 16-bit and 8-bit ISA Bus with indexing I/O via a standard AT edge connector. External logic has been added to provide signals which the SED1352 does not support directly. See Application Note X16-AN-003-xx. Note 1. This board has been designed to operate in conjunction with either a VGA card or monochrome card, or as a standalone card. If using the SDU1352B0C in conjunction with a VGA display adapter the following limitations apply: a. Only 64K bytes of memory is available, residing at the D000h segment. b. Given the memory limitation certain panel size and gray shade capabilities are reduced. c. The VGA card video BIOS must be 8-bit only. The SDU1352B0C must be configured as follows: SW1-1 open : 8-bit operation, necessary to prevent MEMCS16# conflict when reading VGA BIOS SW1-2 to 7 : set as desired SW1-8 closed : 64K bytes available at D000h segment JP1 2-3 shorted : to reflect SW1-8 polarity If using the SDU1352B0C in conjunction with a monochrome display adapter all 128K bytes of memory is available residing at segment C000h - D000h. The SDU1352B0C can be used as a stand-alone video adapter with 128K bytes memory available. If used as a standalone video adapter the BIOS setup program for the computer must support and have "No Video" selected as the video adapter. The BIOS1352.COM utility program can be used with the evaluation board to simulate a standard video BIOS, thus providing text and cursor functionality. See the BIOS1352.COM Utility manual, X16-UI-003-xx for details. 2. This board is pre-set to use indexing I/O with address 000 0011 0??? 000x, where x is don't care and ??? can be configured through dip-switch SW1-7 to SW1-5. The factory setting of ??? = 001, i.e., I/O address = 0310h and 0311h. 3. In indexing I/O, only two I/O address spaces are needed. For example, if I/O address 310h is used, 310h will be the index register and 311h will be the data register. Example: I/O I/O I/O I/O write 310h 01 read 311h write 310h 05 write 311h 07 :set index = 1 :read contents of AUX[01h] :set index = 5 :write 07 to AUX[05h] SED1352 X16-AN-002-09 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 Epson Research and Development Vancouver Design Center Page 13 1.3.2 Non-ISA Bus Support This evaluation board was specifically designed to support the standard 8-/16-bit ISA bus. However, as the SED1352 does support other bus interfaces, header strips have been provided containing all necessary I/O pins (see section 1.3.9 on page 14). When using the header strips to provide the bus interface observe the following: 1. 2. All I/O signals on the ISA bus card edge must be isolated from the ISA Bus (do not plug the card into a computer). Voltage lines are provided on the header strips. U2, a TIBPAL22V10, is currently used to provide the SED1352 IOCS# (pin 23) and MEMCS# (pin 22) input signals for ISA bus use. This functionality must now be provided externally and these two pins need to disconnected as there may be conflict problems associated with two different outputs driving the same input. 1.3.3 SRAM Support The SDU1352B0C board supports 16-bit wide, 64K byte - 128K byte SRAM only. DIP switch SW1-8 selects between the two options. 1.3.4 Monochrome LCD Support The SED1352 supports 4- and 8-bit Dual and Single monochrome STN LCD panels. All the necessary signals are provided on the 40-pin ribbon cable header. The interface signals are alternated with grounds on the cable to reduce cross talk and noise related problems. Refer to Table 1-4, "LCD Signal Connector J1 Pinout," on page 9 for specific settings. 1.3.5 Power Save Modes The SED1352 supports 2 software Power Save Modes. The utility program 1352PD.EXE is supplied to control the software modes. The software modes are controlled by directly writing the SED1352 associated internal registers. 1.3.6 Adjustable LCD Panel Negative Power Supply The majority of Monochrome LCD panels require a negative power supply to provide between -18 V and -23 V (Iout=45mA). For ease of implementation, such a power supply has been provided as an integral part of this design. The signal VLCD can be adjusted by R11 (100K potentiometer) to provide an output voltage from -14 V to -23 V and is enabled/disabled by the control signal LCDENB. Note LCDENB is directly controlled by register AUX[01], bit 4, of the SED1352. The VLCD power supply used on the SDU1352 requires a logic "1" to disable it. As the signal LCDENB is a logic "0" at power-up, it is inverted by external logic to disable VLCD and prevent damaging the panel connected to the SDU1352. Determine the panel's specific power requirements and set the potentiometer accordingly before connecting the panel. SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 SED1352 X16-AN-002-09 Page 14 Epson Research and Development Vancouver Design Center 1.3.7 Adjustable LCD Panel Positive Power Supply Most single Monochrome 640x480 STN LCD panels require a positive power supply to provide between +23V and +40V (Iout=45mA). For ease of implementation, such a power supply has been provided as an integral part of this design. The signal VDDH can be adjusted by R8 (100K potentiometer) to provide an output voltage from +23 V to +40 V and is enabled/disabled by the control signal LCDENB. Note LCDENB is directly controlled by register AUX[01], bit 4, of the SED1352. The VDDH power supply used on the SDU1352 requires a logic "1" to disable it. As the signal LCDENB is a logic "0" at power-up, it is inverted by external logic to disable VLCD and prevent damaging the panel connected to the SDU1352. Determine the panel's specific power requirements and set the potentiometer accordingly before connecting the panel. 1.3.8 Crystal Support The input crystal frequency may be up to 25.175MHz depending on the specific panel size and frame rate desired. Refer to Section 9.3 of the SED1352 Functional Specification, Drawing Office No. X16-SP-001-xx for further details. 1.3.9 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of SED1352 are connected to the header strips H1 and H2 for easy interface to a CPU/Bus other than the ISA bus. Refer to Table 1-5, "CPU/BUS Connector H1 Pinout," on page 10 and Table 1-6, "CPU/BUS Connector H2 Pinout," on page 11 for specific settings. Note These headers only provide the CPU/Bus interface signals from SED1352, when MC68K interface is selected (SW1-3 closed), external decoding logic MUST be used to access the SED1352. 1.3.10 Schematic Notes The evaluation boards may have been modified and therefore the following schematics may not reflect the actual implementation. Please request updated information before starting any hardware design. SED1352 X16-AN-002-09 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 Epson Research and Development Vancouver Design Center Page 15 Appendix A PARTS LIST Item # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Qty/ Board 33 1 2 4 2 1 19 1 2 1 1 7 4 2 4 1 1 1 2 1 2 1 1 2 2 2 1 2 2 2 1 1 1 Designation C1, C8-C10, C14-C42 C2 C3, C4 C7, C11 - C13 H1, H3 H2 JP1 - JP19 J1 J2, J3 Q1 Q2 R1, R3-R8 R2, R15, R18, R21 R9 , R10 R11 - R14 R16 R17 R19 R20, R22 R24 S1, S2 S3 U1 U4, U5 U8, U9 U10, U11 U12 U13, U14 U15, U16 U17, U18 U19 U20 U21 Part Value 0.1uF 1.0uF/35V 56uF/35V 10uF/15V Con32A Con36A Header 3 Con40A M68340EVSP-64A 2N3905 2N3903 1 ohm 1K 10K 1206 pckg Tantalum .1 spacing radical LXF35VB56RM6X11LL Tantalum D-SIZE 0.1" 2x16 Male Header (PTH) 0.1" 2x18 Male Header (PTH) 0.1" 1x3 Male Header (PTH) 40 pin strouded header dual-row-center key Socket strip/wire wray 64 pin #100-064-451 PNP Signal Transistor (TO-92 PTH) NPN Signal Translator (TO-92 PTH) 1206 pckg /1% 1206 pckg /5% Description 9 resistors resistor-network : Bourne 4610-101-103 (or equivalent) 10K 1206 pckg /5% 100 ohm 1206 pckg /5% 500 ohm Trim Pot Bourns 3386W-1-501 (or equivalent) 100K Trim Pot Bourns 3386W-1-104 (or equivalent) 100K 1206 pckg / 5% 240 ohm 1206 pckg / 5% SW DIP-8 Dip Switch 8 position SW DIP-4 Dip Switch 4 position SED1352F QFP5-100 / 100 pin SOCKET Supplied by SMOS 100ns 32K byte Static RAM - SMOS part number SRM20256LM10 (SOP2 SMT) 74LS688 DW020 SMT TIBPAL22V10-15BCNT SOCKET + Component programmed by SMOS 74LS09 D014 SMT SN74LVT16244 SN74LVT16244 (SSOP) SN74LVT16245 SN74LVT16244 (SSOP) 74HCT244 DW020 SMT LM317T 3-pin TO-220 regulator XENTECK - Negative Power Supply Supplied by EPN001 SMOS OSC-14 SOCKET Only SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 SED1352 X16-AN-002-09 Page 16 Appendix B SDU1352B0C REV. 1.0 SCHEMATIC DIAGRAMS SED1352 X16-AN-002-09 U1 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 LD0 LD1 LD2 LD3 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 YD LP WF XSCL LCDENB UD0 UD1 UD2 UD3 YD LP WF XSCL LCDENB 78 79 80 81 82 YD LP WF XSCL LCDENB 73 72 71 70 UD0 UD1 UD2 UD3 77 76 75 74 LD0 LD1 LD2 LD3 BHE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# OSC1 OSC2 /SBHE /IOCS /IOW /IOR /MEMCS /SMEMW /SMEMR OSC1 OSC2 92 93 87 88 89 84 85 86 91 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 94 95 96 97 98 99 100 1 4 5 6 7 8 9 10 11 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD[0..15] RESET RESET 32 VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VA8 VA9 VA10 VA11 VA12 VA13 VA14 VA15 33 34 35 36 37 38 39 40 41 42 43 62 63 64 65 66 VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VA8 VA9 VA10 VA11 VA12 VA13 VA14 VA15 VA[0..15] +5V VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 3 53 VDD VDD VSS VSS READY 90 SED1352F 2 52 VWE# VOE# VCS0# VCS1# 67 83 68 69 /VWE /VOE /VCS0 /VCS1 IOCHRDY 44 45 46 47 48 49 50 51 54 55 56 57 58 59 60 61 VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD[0..15] /VWE /VOE /VCS0 /VCS1 IOCHRDY S-MOSSYSTEMSINC.(VDC) Title SDU1352BOC Size B Date: DocumentNumber X16-SCH-002 December13,1995 Sheet 1 of REV 1.0 7 SA[0..19] /SBHE /IOCS /IOW /IOR /MEMCS /SMEMW /SMEMR OSC1 OSC2 Figure 1: SDU1352B0C Rev. 1.0 Schematic Diagram (1 of 7) RESET +12V +12V +5V +5V Epson Research and Development Vancouver Design Center SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 VSS GND SA[1..19] U2 /IODC1TO9 /IOCS16EN /LCDENB LCDENB /IOEN REFRESH LCDENB /IOEN REFRESH +5V 24 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 12 GND TIBPAL22V10 VCC CLK/IN IN IN IN IN IN IN IN IN IN IN /IOCS /MEMCS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN 1 2 3 4 5 6 7 8 9 10 11 23 22 21 20 19 18 17 16 15 14 13 128K=0FORUSINGALL128K 128K=1FORUSINGUPPER64K FROMSW1-8 128K R2 100K +5V U3 P=Q 19 Epson Research and Development Vancouver Design Center 128K +5V JP4 3 2 1 ADDBIT6 ADDBIT5 ADDBIT4 HEADER3 SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 2 4 6 8 11 13 15 17 P0 P1 P2 P3 P4 P5 P6 P7 +5V R1 1K U5A 1 3 2 74LS09 U5B 4 I/OADDRESS=0000110???000X 5 74LS09 +5V 9 U4 /8BITBI P=Q 19 10 74LS09 8 /MEMCS16 U5C 6 /IOCS16 /LCDPWR SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 G 74LS688 SA1 1 3 5 7 9 12 14 16 18 LA17 LA18 LA19 LA20 LA21 LA22 LA23 2 4 6 8 11 13 15 17 P0 P1 P2 P3 P4 P5 P6 P7 U5D 12 11 13 74LS09 Unusedgate 3 5 7 9 12 14 16 18 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 G 74LS688 MEMORYADDRESS=CSEGMENTORC&DSEGMENTS 1 S-MOSSYSTEMS,INC.(VDC) Title SDU1352B0C Size B Date: DocumentNumber X16-SCH-002 December12,1995 Sheet 2 of REV 1.0 7 JP3 3 2 1 HEADER3 JP2 3 2 1 HEADER3 JP1 3 2 1 HEADER3 16-BITINTERFACE=1 Figure 2: SDU1352B0C Rev. 1.0 Schematic Diagram (2 of 7) 8-BITINTERFACE=0 LA[17..23] +12V +12V +5V +5V SED1352 X16-AN-002-09 VSS GND Page 17 Page 18 +5V SED1352 X16-AN-002-09 11111111 R3 10K 23456789 1 0 R4 10K R5 10K R6 10K R9A 10K R9H 10K R9I 10K 1 1111111 65432109 S1 SWDIP-8 12345678 128k VD9 VD8 VD7 VD3 VD2 VD1 VD0 (IOBIT6) (IOBIT5) (IOBIT4) (NOBYTESWAP) (ISA) (INDEXING) (8BITBI) 128k VD11 VD12 VD14 VD15 VD[0..15] U6 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 21 22 23 25 26 27 28 29 VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 21 22 23 25 26 27 28 29 U7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 +5V +5V NC OE WE CS1 CS2 VDD VSS 8 24 SRM20100LTM-70 /VOE /VWE /VCS0 /VCS1 9 32 5 30 6 VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VA8 VA9 VA10 VA11 VA12 VA13 VA14 VA15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC OE WE CS1 CS2 VDD VSS SRM20100LTM-70 9 8 24 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 32 5 30 6 20 19 18 17 16 15 14 13 3 2 31 1 12 4 11 7 10 VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VA8 VA9 VA10 VA11 VA12 VA13 VA14 VA15 20 19 18 17 16 15 14 13 3 2 31 1 12 4 11 7 10 +5V S-MOSSYSTEMSINC.(VDC) Title SDU1352BOC Size B Date: DocumentNumber X16-SCH-002 December8,1995 Sheet 3 of REV 1.0 7 VD[0..15] VA[0..15] Figure 3: SDU1352B0C Rev. 1.0 Schematic Diagram (3 of 7) +5V /VOE /VWE /VCS0 /VCS1 +12V +12V +5V +5V Epson Research and Development Vancouver Design Center SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 VSS GND MonoLCDConnector J1 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 XSCL LP YD CON40A LP YD WF /LCDPWR Epson Research and Development Vancouver Design Center SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 XSCL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VLCD +5V +12V VDDH WF /LCDPWR 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 H1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 SD1 SD3 GND SD5 SD7 GND SD9 SD11 GND SD13 SD15 GND GND +12V IOCHRDY /MEMCS SA0 SA2 SA4 SA6 GND SA8 SA10 SA12 GND SA14 SA16 SA18 GND +5V /IOW /SMEMW CON32A H2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 CON32A SA1 SA3 SA5 SA7 GND SA9 SA11 SA13 GND SA15 SA17 SA19 GND +5V /IOR /SMEMR CPU/BUSI/F S-MOSSYSTEMSINC.(VDC) Title SDU1352BOC Size B Date: DocumentNumber X16-SCH-002 December7,1995 Sheet 4 of REV 1.0 7 Figure 4: SDU1352B0C Rev. 1.0 Schematic Diagram (4 of 7) SD0 SD2 GND SD4 SD6 GND SD8 SD10 GND SD12 SD14 RESET GND +12V /SBHE /IOCS +12V +12V +5V +5V VSS GND SED1352 X16-AN-002-09 Page 19 Page 20 SED1352 X16-AN-002-09 +5V AT1 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 RESET +12V /SMEMW /SMEMR /IOW /IOR AT2 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 REFRESH ATCON-A ATCON-B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 /IOCHCK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 GND RESET +5V IRQ9 -5V DRQ2 -12V OWS +12V GND /SMEMW /SMEMR /IOW /IOR /DACK3 DRQ3 /DACK1 DRQ1 /REFRESH CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 /DACK2 T/C BALE +5V OSC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AT3 LA23 LA22 LA21 LA20 LA19 LA18 LA17 AT4 /MEMCS16 /IOCS16 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 ATCON-C ATCON-D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 /SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 /MEMR /MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 +5V /MEMCS16 /IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 /DACK0 DRQ0 /DACK5 DRQ5 /DACK6 DRQ6 /DACK7 DRQ7 +5V MASTER GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 S-MOSSYSTEMSINC.(VDC) Title SDU1352BOC Size B Date: DocumentNumber X16-SCH-002 December8,1995 Sheet 5 of REV 1.0 7 IOCHRDY /IOEN SA[0..19] /SBHE LA[17..23] Figure 5: SDU1352B0C Rev. 1.0 Schematic Diagram (5 of 7) SD[0..15] +12V +12V +5V +5V Epson Research and Development Vancouver Design Center SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 VSS GND U8 RD-0412 D C _ I N GGGGGGG NNNNNNN DDDDDDD 3 VDDH 1uH adjustable23vto40v C1 56uF/35V R7 470K 11 4567801 1 L1 1 2 +5V 2 R E M O T E D C _ O U T V O U T _ A ND C9 J Epson Research and Development Vancouver Design Center 3 R8 200k 2 1 C2 10uF/63V LOWESR C3 10uF/63V LOWESR C4 10uF/63V SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 R10 14k +5V R13 2 1K U9 EPN001 Q1 32N3905 1 D C _ I N GG NN DD R12 6 54 2 1 100K +5V 1 3 R11 100K 2 1 C5 56uF/35V C6 56uF/35V 3 Q2 2N3903 VLCD adjustable-18vto-23v 2 11 10 D C _ I N V O U T _ A D J D C _ O NNNN U C9 C7 C8 C3 T D C _ O U T R14 1K R15 100K S-MOSSYSTEMSINC.(VDC) Title SDU1352BOC Size B Date: DocumentNumber X16-SCH-002 December12,1995 Sheet 6 of REV 1.0 7 Figure 6: SDU1352B0C Rev. 1.0 Schematic Diagram (6 of 7) /LCDPWR +12V +12V +5V +5V VSS GND SED1352 X16-AN-002-09 Page 21 Page 22 SED1352 X16-AN-002-09 +5V U10 1 NC VCC GND 7 OUT OSC-14 Whentheoscillatorpackageis used,thestabilizingcapacitors andresistormustberemoved. 14 OSC1 4 R16 2M Y1 1 25.175Mhz 8 OSC2 C7 7pF C8 7pF BYPASSCAPACITORS(1/POWERPIN) C12 .1uF C13 .1uF C14 .1uF C15 .1uF C16 .1uF C17 .1uF C18 .1uF C19 .1uF C20 .1uF C21 .1uF C22 .1uF +5V +12V C9 10uF C10 10uF S-MOSSYSTEMS,INC.(VDC) Title SDU1352B0C Size B Date: DocumentNumber X16-SCH-002 December8,1995 Sheet 7 of REV 1.0 7 +5V Figure 7: SDU1352B0C Rev. 1.0 Schematic Diagram (7 of 7) C11 .1uF +12V +12V +5V +5V Epson Research and Development Vancouver Design Center SDU1352B0C Rev. 1.0 Evaluation Board User Manual Issue Date: 98/10/07 VSS GND SED1352 Dot Matrix Graphics LCD Controller Power Consumption Document Number: X16-AN-006-06 Copyright (c) 1995, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-006-06 Power Consumption Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 1 SED1352 POWER CONSUMPTION 1.1 Conditions 1. 2. 3. 4. Pixel clock = 25MHz: screen pattern = 00h and AAh on 640x480 single panel. Pixel clock = 12MHz: screen pattern = 00h and AAh on 480x320 single panel. Pixel clock = 6MHz: screen pattern = 00h and AAh on 320x240 single panel. No display connected. SED1352 Power Consumption (VDD = 5.0V) 100 80 Power (mW) 25MHz Pixel Clock 12MHz Pixel Clock 60 6MHz Pixel Clock 40 20 0 ACTIVE Pattern 00h ACTIVE Pattern AAh PD1 PD2 Operating Mode Active Pattern 00h Active Pattern AAh PD1 14.3 11.8 4.7 PD2 0.1 0.1 0.0 Units mW mW mW 25MHz 12MHz 6MHz 93.0 58.7 32.7 105.5 66.1 36.1 Power Consumption Issue Date: 98/10/08 SED1352 X16-AN-006-06 Page 4 Epson Research and Development Vancouver Design Center SED1352 Power Consumption (VDD = 3.0V) 40 35 30 25MHz Pixel Clock 25 Power (mW) 12MHz Pixel Clock 6MHz Pixel Clock 20 15 10 5 0 ACTIVE Pattern 00h ACTIVE Pattern AAh PD1 PD2 Operating Mode Active Pattern 00h Active Pattern AAh PD1 3.3 2.2 0.2 PD2 0.2 0.3 0.0 Units mW mW mW 25MHz 12MHz 6MHz 35.0 16.1 8.3 41.2 18.1 9.5 SED1352 X16-AN-006-06 Power Consumption Issue Date: 98/10/08 SED1352F0B Dot Matrix Graphics LCD Controller ISA Bus Interface Considerations Document Number: X16-AN-003-05 Copyright (c) 1995, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B X16-AN-003-05 ISA Bus Interface Considerations Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 16-BIT ISA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 1.3 1.4 PAL Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Discrete Logic Description . . . . . . . . . . . . . . . . . . . . . . . . 7 SED1352F0B Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.1 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2 Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 8-BIT ISA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 SED1352F0B Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.1 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.2 Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 List of Figures Figure 8: 16-Bit ISA Bus Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 9: 8-Bit ISA Bus Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ISA Bus Interface Considerations Issue Date: 98/10/08 SED1352F0B X16-AN-003-05 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B X16-AN-003-05 ISA Bus Interface Considerations Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 5 1 INTRODUCTION The SED1352F0B is a general purpose LCD controller capable of interfacing to a variety of microprocessors. This interface is accomplished through the use of minimal external circuitry. This application note describes the interface between the SED1352F0B and the ISA Bus. 1.1 Reference Material Refer to the SED1352F0B Hardware Functional Specification (X16-SP-001-xx) for complete AC timing details. This document makes no attempts to describe the operation of the ISA Bus, please refer to the appropriate ISA Bus documentation for complete information. ISA Bus Interface Considerations Issue Date: 98/10/08 SED1352F0B X16-AN-003-05 Page 6 Epson Research and Development Vancouver Design Center 2 16-BIT ISA BUS INTERFACE For the purpose of the example shown below, the following conditions are set by default: 1. 2. Indexing I/O with addresses 0310h and 0311h (see Configuration Options) 128Kbytes of display memory occupying $C and $D segments (see Configuration Options) Note This memory configuration will conflict with a VGA card installed on the same bus, therefore either a serial terminal or monochrome display adapter is recommended as the primary console. This section provides the necessary equations and settings to complete the interface between the SED1352F0B and the 16-bit ISA Bus. Note A PAL was used instead of discrete logic to reduce external component count. 16-Bit ISA Bus AEN REFRESH SA1-15 SA0-19 SBHE# SD0-15 SMEMW# SMEMR# IOW# IOR# IOCHRDY 1 IOCS16# LA17-23 4 MEMCS16# 6 3 SED1352F0B IOCS# VCC PAL MEMCS# 10k AB0-19 BHE# DB0-15 MEMW MEMR IOW# IOR# READY VD0,VD7, VD11-12, VD14-15 A 2 IOCS16EN B P 5 Q LA23-17 (p0-6) 0000110 (q0-6) 74LS09 G 74LS688 Figure 8: 16-Bit ISA Bus Implementation SED1352F0B X16-AN-003-05 ISA Bus Interface Considerations Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 7 1.2 PAL Equations The PAL is programmed with the following equations: 1. As stated above, the default I/O address is from 0310h to 0311h. The SED1352F0B provides internal decoding of address bits A0 to A9, therefore minimal external circuitry is necessary to provide signals IOCS# and IOCS16# IOCS# is required by the SED1352 to indicate a valid IO cycle. In an ISA bus environment, valid IO decoding must include addresses A15-A0. Given this example, addresses A10-15 must all be '0' and AEN must also be '0'. IOCS# = !(!AEN & !A15 & !A14 & !A13 & !A12 & !A11 & !A10) 2. As the SED1352 is capable of 16-bit IO access, the IOCS16# bus signal must be driven externally to indicate such a cycle. As stated in the ISA specification, the IOCS16# is a straight address decode without qualification. IOCS16EN# = !(!IOCS# & A9 & A8 & !A7 & !A6 & !A5 & A4 & !A3 & !A2 & !A1) 3. With 128Kbytes of display memory and A17 to A19 decoded internally to SED1352F0B; MEMCS# = !REFRESH 1.3 Additional Discrete Logic Description 1. 2. As shown in Figure 1, the 74LS688 is configured as a memory decoder with valid addresses between 0Cxxxxh and 0Dxxxxh. The 74LS09 is used simply to provide the Open-Collector outputs necessary for the IOCS16# and MEMCS16# signals. 1.4 SED1352F0B Default Setup 1.4.1 Configuration Options 1. 2. 3. 4. 5. 6. VD15 - VD13 = 110 VD12 - VD4 = 110001000 VD3 = 0 VD2 = 0 VD1 = 0 VD0 = 1 memory decoding for locations $C and $D segments I/O decoding for locations 1100010000b - 1100010001b no byte swap of high and low bytes ISA Bus interface, i.e. non- MC68K interface indexing I/O 16-bit bus interface Where 1 = pull-up with a 10K resistor; 0 = no pull-up resistor Note The states of these data pins are internally latched during RESET. 1.4.2 Register Setting AUX[1] bit 1 = 0 for 16-bit memory interface (must be 16-bit with a 16-bit bus). ISA Bus Interface Considerations Issue Date: 98/10/08 SED1352F0B X16-AN-003-05 Page 8 Epson Research and Development Vancouver Design Center 3 8-BIT ISA BUS INTERFACE For the purpose of the example shown below, the following conditions are set by default: 1. Indexing I/O with partial decoding, i.e. address lines A10 to A15 are not decoded for I/O cycles Note Partial decoding is quite safe on most ISA Bus systems as I/O addresses above 03FFh are rarely used. 2. 3. I/O addresses are xxxxxx1100000000b and xxxxxx1100000001b 64Kbytes of display memory occupying $A segment Note The 74LS00 is simply used to detect the $B segment and invalidate the MEMCS# input. Note This memory configuration will conflict with a VGA card installed on the same bus, therefore either a serial terminal or monochrome display adapter is recommended as the primary console. This section provides the necessary settings to complete the interface between the SED1352F0B and the 8-bit ISA Bus. Since I/O addresses are partially decoded, there is no need to use a PAL for decoding. 8-Bit ISA Bus AEN REFRESH SA16 SA0-19 1 4 5 3 SED1352F0B IOCS# BHE# VCC B 6 2 A MEMCS# VD11-13, VD15 10k 74LS00 AB0-19 SD0-7 SMEMW# SMEMR# IOW# IOR# IOCHRDY DB0-7 MEMW MEMR IOW# IOR# READY Figure 9: 8-Bit ISA Bus Implementation SED1352F0B X16-AN-003-05 ISA Bus Interface Considerations Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 9 1.5 SED1352F0B Default Setup 1.5.1 Configuration Options 1. 2. 3. 4. 5. 6. VD15 - VD13 = 101 VD12 - VD4 = 110000000 VD3 = 0 VD2 = 0 VD1 = 0 VD0 = 0 memory decoding for locations $A segment I/O decoding for locations 1100000000b - 1100000001b No byte swap of high and low bytes ISA Bus interface, i.e. non- MC68K interface Indexing I/O 8-bit bus interface Where 1 = pull-up with a 10K resistor; 0 = no pull-up resistor Note The states of these data pins are internally latched during RESET. 1.5.2 Register Setting AUX[1] bit 1 = 0 for 16-bit memory interface or AUX[1] bit 1 = 1 for 8-bit memory interface. ISA Bus Interface Considerations Issue Date: 98/10/08 SED1352F0B X16-AN-003-05 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B X16-AN-003-05 ISA Bus Interface Considerations Issue Date: 98/10/08 SED1352 Dot Matrix Graphics LCD Controller MC68340 Interface Considerations Document Number: X16-AN-004-06 Copyright (c) 1996, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-004-06 MC68340 Interface Considerations Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MC68340 MPU INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 2.3 MC68340 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 PAL Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SED1352 Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Figures Figure 1: MC68340 MPU Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MC68340 Interface Considerations Issue Date: 98/10/08 SED1352 X16-AN-004-06 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-004-06 MC68340 Interface Considerations Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 5 1 INTRODUCTION The SED1352 is a general purpose LCD controller capable of interfacing to a variety of microprocessors. This interface is accomplished through the use of minimal external circuitry. This application note describes the interface between the SED1352 and the 16-bit MC68340 microcontroller. 1.1 Reference Material Refer to the SED1352 Hardware Functional Specification (X16-SP-001-xx) for complete AC timing details. This document makes no attempts to describe the operation of the MC68340 microcontroller, please refer to the appropriate MC68340 documentation for this information. MC68340 Interface Considerations Issue Date: 98/10/08 SED1352 X16-AN-004-06 Page 6 Epson Research and Development Vancouver Design Center 2 MC68340 MPU INTERFACE The following sections provide the necessary settings and equations to complete the interface between the SED1352 and the MC68340 microcontroller. MC68340 CS3 SIZ0 SED1352 MEMCS# VCC PAL A0 A10-A17 IOCS# BHE# VD0-VD3 VD13 10k A0-A19 D0-D15 AB0-AB19 DB0-DB15 VCC VCC MEMR# MEMW# READY IOR# IOW# RESET 4.7k DSACK1 AS R/W RESET Figure 1: MC68340 MPU Interface Block Diagram 2.1 MC68340 Setup For the purpose of this example, the following conditions apply: The internal chip select signal CS3 of the MC68340, along with external DSACK1 response, is employed to access the SED1352. Direct mapping of the I/O with starting address at 00000000h, and 128Kbytes of display memory with starting address 00020000h are also used. 1. 2. 3. 4. CS3 with 256kbyte block size - starting address at 00000000h and ending address at 0003FFFFh External DSACK1 response - 16-bit port Don't care Function Codes and with CPU space access Both read and write accesses are allowed Settings for the Address Mask register and Base Address register for the above conditions are: 058h - 05Bh 05Ch - 05Fh = 0003FFFFh = 000000F5h Address Mask register Base Address register SED1352 X16-AN-004-06 MC68340 Interface Considerations Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 7 2.2 PAL Equations The PAL is programmed with the following equations: 1. With direct-mapping I/O occupying locations from 00000000h to 0000000Fh and A4 to A9 decoded internally to SED1352; IOCS# = !(!CS3 & !A17 & !A16 & !A15 & !A14 & !A13 & !A12 & !A11 & !A10) With memory locations from 00020000h to 003FFFFh and A17 to A19 decoded internally to SED1352; MEMCS# = CS3 BHE# becomes valid for two conditions: 1. 16-bit or 32-bit cycle, i.e., SIZ0=0 2. 8-bit cycle with odd byte access, i.e., SIZ0=1 and A0=1; BHE# = SIZ0 & !A0 2. 3. 2.3 SED1352 Default Setup Configuration Options 1. 2. 3. 4. 5. 6. VD15 - VD13 = 001 VD12 - VD4 = 000000xxx VD3 = 1 VD2 = 1 VD1 = 1 VD0 = 1 memory decoding for locations 20000h - 3FFFFh I/O decoding for locations 0000000000b - 0000001111b byte swap of high and low bytes MC68K interface direct-mapping I/O 16-bit bus interface Where x = don't care; 1 = pull-up with a 10K resistor; 0 = no pull-up resistor Note The states of these data pins are internally latched during RESET. Register Setting AUX[01h] bit 1 = 0 for 16-bit memory interface (must be 16-bit with a 16-bit bus). MC68340 Interface Considerations Issue Date: 98/10/08 SED1352 X16-AN-004-06 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-004-06 MC68340 Interface Considerations Issue Date: 98/10/08 SED1352 Dot Matrix Graphics LCD Controller LCD Panel Options / Memory Requirements Document Number: X16-AN-005-07 Copyright (c) 1995, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-005-07 LCD Panel Options / Memory Requirements Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 CONFIGURATION EQUATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 Input Clock Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SRAM Size and Access Time Requirements . . . . . . . . . . . . . . . . . . . . . 6 2.2.1 SRAM Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.2 SRAM Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 8-Bit Display Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.1 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.2 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 16-bit Display Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.1 Configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.2 Register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 List of Figures Figure 1: 8-Bit Memory Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2: 16-Bit Memory Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LCD Panel Options / Memory Requirements Issue Date: 98/10/08 SED1352 X16-AN-005-07 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-005-07 LCD Panel Options / Memory Requirements Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 5 1 INTRODUCTION The SED1352 is a highly configurable general purpose LCD controller. The LCD panel frame-rate, resolution, and gray shades all determine the memory and input clock requirements. This application note will describe the equations used to determine the various parameters. An example resolution and desired frame-rate will be selected and used to determine the remaining variables. 1.1 Reference Material Refer to the SED1352 Hardware Functional Specification (X16-SP-001-xx) for complete AC timing details. LCD Panel Options / Memory Requirements Issue Date: 98/10/08 SED1352 X16-AN-005-07 Page 6 Epson Research and Development Vancouver Design Center 2 CONFIGURATION EQUATIONS 2.1 Example: LCD panel resolution: LCD panel configuration LCD Gray Shades Desired Frame-rate: 640x240 4 bit, Single drive panel 4 ~70Hz 2.1.1 Input Clock Requirement For a frame rate of 70Hz, the input clock (or pixel clock) frequency can be calculated as following, fOSC = input clock fOSC = Frame Rate * (# of horizontal pixels + 16) * (# of vertical lines + 4) Therefore; fOSC = 70 * (640 + 16) * (240 + 4) fOSC = 11.2MHz Note 1. Due to oscillator frequency availability, a 12MHz oscillator is selected thus producing a slightly higher frame-rate (~75Hz). 2. For a detailed description of the frame rate formula, see section 9.3 of the SED1352 Hardware Functional Specification, drawing office number X16-SP-001-xx. 2.2 SRAM Size and Access Time Requirements 2.2.1 SRAM Size Memory Size (bytes) = (# of Horizontal pixels)* (# of Vertical pixels) 8 (# of bits/pixel) i.e., 4 gray shades = 2 bits / pixel, therefore 1 byte (8 bits) = 4 pixels Therefore: Memory size (bytes) = (640 * 240) / 4 Memory size (bytes) = 37.5 K bytes. Note For a detailed description of the memory size requirement, see section 9.4 of the SED1352 Hardware Functional Specification, drawing office number X16-SP-001-xx. / SED1352 X16-AN-005-07 LCD Panel Options / Memory Requirements Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 7 2.2.2 SRAM Access Time For 8-bit display memory interface; Access time < 2/fOSC - 50. With 12MHz input clock; Access time < 116ns. For 16-bit display memory interface; Access time < 4/fOSC - 50. With 12MHz input clock, access time < 283ns. Note For detail description of the SRAM access time, see section 9.2 of the SED1352 Hardware Functional Specification, drawing office number X16-SP-001-xx. LCD Panel Options / Memory Requirements Issue Date: 98/10/08 SED1352 X16-AN-005-07 Page 8 Epson Research and Development Vancouver Design Center 3 IMPLEMENTATION 3.1 8-Bit Display Memory Interface Since 35.7K bytes with at least 116ns access time SRAM is required, one 8K bytes SRAM with 100ns access time, and one 32K bytes SRAM with 100ns access time are used in this example. 640x240 Panel UD0-3 LD0-3 YD LP XSCL WF SRM20256-10 D0-7 A0-14 CS 12MHz OSC1 VD0-7 VA0-14 VCS0# VCS1# 32KB OE WE VOE# VWE# SED1352 D0-7 A0-12 CS1 OE 8KB WE VCC CS2 SRM2264-10 Figure 1: 8-Bit Memory Configuration Example 3.1.1 Configuration Options VD0 selects 16/8-bit Bus interface. When using a 8-bit memory interface, the 8-bit Bus interface must also be selected. The state of VD0 is internally latched during RESET. In this example VD0 has no external pull-up resistor and is therefore latched as a '0' during RESET (due to the internal pull-down resistors) thus selecting the 8-bit Bus interface. Other option settings are not related to this implementation. SED1352 X16-AN-005-07 LCD Panel Options / Memory Requirements Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 9 3.1.2 Register Settings AUX[00h] = 0000 0000 AUX[01h] = 1001 0011 AUX[02h] = 1001 1111 AUX[03h] = 0000 0000 AUX[04h] = 1110 1111 AUX[05h] = 0000 0000 AUX[06h] = 0000 0000 AUX[07h] = 0000 0000 AUX[08h] = xxxx xxxx AUX[09h] = xxxx xxxx AUX[0Bh] = xxxx xx00 default starting address at 0000h (with AUX[06h]) don't care when not using split screen don't care when not using split screen AUX[04h] when not using split screen not in test mode 4-bit single panel, 4 gray shades, 8-bit display memory interface with 32K bytes is the first chip horizontal resolution = 640 ; 4 gray shades = 4 pixels per byte ; 4 pixels per fetch not in power save modes total 240 scan lines WF = 0 AUX[0Ah] = 1110 1111 together with AUX[0Bh] bit1-0, should be the same as or larger than AUX[05h] bit1-0 and AUX[0Dh] = 0000 0000 no virtual screen Example setting of Look-up Table when using bank# 0 for display: AUX[0Eh] = 00xx 0000 AUX[0Fh] = xxxx 0000 AUX[0Eh] = 00xx 0001 AUX[0Fh] = xxxx 0101 AUX[0Eh] = 00xx 0010 AUX[0Fh] = xxxx 1010 AUX[0Eh] = 00xx 0011 AUX[0Fh] = xxxx 1111 x = don't care index = 0 gray = 0 index = 1 gray = 5 index = 2 gray = A index = 3 gray = F LCD Panel Options / Memory Requirements Issue Date: 98/10/08 SED1352 X16-AN-005-07 Page 10 Epson Research and Development Vancouver Design Center 3.2 16-bit Display Memory Interface Since 35.7K bytes with at least 283ns access time SRAM is required, two 32K bytes SRAM with 120ns access time are used for this example. 640x240 Panel UD0-3 LD0-3 YD LP XSCL WF SRM20256-12 VD0-7 D0-7 A0-14 CS 12MHz OSC1 VD0-15 VA0-14 VCS0# VCS1# 32KB OE WE VOE# VWE# VD8-15 SED1352 D0-7 A0-14 CS OE 32KB WE SRM20256-12 Figure 2: 16-Bit Memory Configuration Example 3.2.1 Configuration options VD0 = no pull-up resistor for 8-bit bus interface or VD0 = pull-up (with a 10K resistor) for 16-bit bus interface. Other option settings are not related to this implementation. SED1352 X16-AN-005-07 LCD Panel Options / Memory Requirements Issue Date: 98/10/08 Epson Research and Development Vancouver Design Center Page 11 3.2.2 Register settings AUX[00h] = 0000 0000 AUX[01h] = 1001 000x AUX[02h] = 0100 1111 AUX[03h] = 0000 0000 AUX[04h] = 1110 1111 AUX[05h] = 0000 0000 AUX[06h] = 0000 0000 AUX[07h] = 0000 0000 AUX[08h] = xxxx xxxx AUX[09h] = xxxx xxxx AUX[0Ah] = 1110 1111 AUX[0Bh] = xxxx xx00 AUX[0Dh] = 0000 0000 not in test mode 4-bit single panel, 4 gray shades, 16-bit display memory interface horizontal resolution = 640 ; 4 gray shades = 4 pixels per byte ; 8 pixels per fetch not in power save modes total 240 scan lines WF = 0 default starting address at 0000h (with AUX[06h]) don,t care when not using split screen don,t care when not using split screen together with AUX[0Bh] bit1-0, should be the same as or larger than AUX[05h] bit1-0 and AUX[04h] when not using split screen no virtual screen Example setting of Look-up Table when using bank# 2 for display: AUX[0Eh] = 10xx 1000 AUX[0Fh] = xxxx 0000 AUX[0Eh] = 10xx 1001 AUX[0Fh] = xxxx 0101 AUX[0Eh] = 10xx 1010 AUX[0Fh] = xxxx 1010 AUX[0Eh] = 10xx 1011 AUX[0Fh] = xxxx 1111 x = don't care Note When LCDENB (bit 4 of AUX[01h]) is used to control the LCD power, the following sequence is recommeded to setup the AUX registers of the SED1352: 1. 2. 3. 4. Write to bit 4 of AUX[01h] with value '0'. Setup the AUX registers accordingly. Delay at least half a second (depend on panel type, it may be required more time delay). Write to bit 4 of AUX[01h] with value '1'. index = 8 gray = 0 index = 9 gray = 5 index = A gray = A index = B gray = F LCD Panel Options / Memory Requirements Issue Date: 98/10/08 SED1352 X16-AN-005-07 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 X16-AN-005-07 LCD Panel Options / Memory Requirements Issue Date: 98/10/08 |
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